Abstract: The invention discloses a chipset having N input/output (I/O) ports coupled to a voltage source which have an observation I/O port. The method includes calculating a first set of impedances at a predetermined frequency or the observation I/O port, if the voltage source is internally coupled to the N I/O ports within the chipset, and calculating a second set of impedances at the predetermined frequency for the observation I/O port, if the voltage source is externally coupled to the N I/O ports through a carrier coupling the core chip to the voltage source. The first set of impedances are compared to the second set of impedances, and the impedance of the power network or the impedance of the carrier is adjusted according to the comparison result.

Abstract: A measuring equipment, such as a vector network analyzer, is provided. The measuring equipment includes a first port and a second port, a probe connected to the first port, an antenna connected to the second port, and a test board corresponding to a type of a device-under-test. A probe-effect is obtained by measuring the test board via the probe and the antenna.

Abstract: The invention discloses a chipset having N input/output (I/O) ports coupled to a voltage source which have an observation I/O port. The method includes calculating a first set of impedances at a predetermined frequency or the observation I/O port, if the voltage source is internally coupled to the N I/O ports within the chipset, and calculating a second set of impedances at the predetermined frequency for the observation I/O port, if the voltage source is externally coupled to the N I/O ports through a carrier coupling the core chip to the voltage source. The first set of impedances are compared to the second set of impedances, and the impedance of the power network or the impedance of the carrier is adjusted according to the comparison result.

Abstract: The present invention provides a signal analyzing method for an electronic device having an on-chip network and an off-chip network. Compared with the conventional signal analyzing method for an electronic device having an on-chip network and an off-chip network, the signal analyzing method of the present invention is able to provide a complete electrical connection and accurate electrical characteristics for an electronic device having an on-chip network and an off-chip network.

Abstract: The invention discloses an impedance design method for a power network of a core chip within a chipset having N input/output (I/O) ports coupled to a voltage source which have an observation I/O port. The method includes calculating a first set of impedances at a predetermined frequency or the observation I/O port, if the voltage source is internally coupled to the N I/O ports within the chipset, and calculating a second set of impedances at the predetermined frequency for the observation I/O port, if the voltage source is externally coupled to the N I/O ports through a carrier coupling the core chip to the voltage source. The first set of impedances to the second set of impedances are compared, and the impedance of the power network or the impedance of the carrier is adjusted according to the comparison result.

Abstract: A circuit board includes a signal line plane and a reference plane. The signal line plane has at least a first transmission line and a second transmission line formed thereon. The reference plane has a conductive region and at least a non-conductive region. The first transmission line and the second transmission line overlap the conductive region in a thickness direction of the circuit board. The non-conductive region includes at least a first part and a second part connected to the first part, where the second part is positioned between the projection of the first transmission line on the reference plane and the projection of the second transmission line on the reference plane, and has no intersection with at least one of the projection of the first transmission line and the projection of the second transmission line.

Abstract: The present invention provides a signal analyzing method for an electronic device having an on-chip network and an off-chip network. Compared with the conventional signal analyzing method for an electronic device having an on-chip network and an off-chip network, the signal analyzing method of the present invention is able to provide a complete electrical connection and accurate electrical characteristics for an electronic device having an on-chip network and an off-chip network.

Abstract: The invention discloses an impedance design method for a power network of a core chip within a chipset having N input/output (I/O) ports coupled to a voltage source which have an observation I/O port. The method includes calculating a first set of impedances at a predetermined frequency or the observation I/O port, if the voltage source is internally coupled to the N I/O ports within the chipset, and calculating a second set of impedances at the predetermined frequency for the observation I/O port, if the voltage source is externally coupled to the N I/O ports through a carrier coupling the core chip to the voltage source. The first set of impedances to the second set of impedances are compared, and the impedance of the power network or the impedance of the carrier is adjusted according to the comparison result.

Abstract: A circuit board includes a signal line plane and a reference plane. The signal line plane has at least a first transmission line and a second transmission line formed thereon. The reference plane has a conductive region and at least a non-conductive region. The first transmission line and the second transmission line overlap the conductive region in a thickness direction of the circuit board. The non-conductive region includes at least a first part and a second part connected to the first part, where the second part is positioned between the projection of the first transmission line on the reference plane and the projection of the second transmission line on the reference plane, and has no intersection with at least one of the projection of the first transmission line and the projection of the second transmission line.

Abstract: An arrangement of non-signal through vias suitable for a wiring board is provided. The wiring board has a contact surface, a core layer and pads. The contact pads are disposed on the contact surface, while the arrangement of non-signal through vias includes first non-signal through vias and a second non-signal through via. The first non-signal through vias pass through the core layer and are electrically connected to some of the contact pads. The second non-signal through via which passes through the core layer is disposed between the first non-signal through vias and is not electrically connected to the contact pads. The interval between the second non-signal through via and anyone of the surrounding first non-signal through vias is smaller than or equal to 0.72 times of the minimum interval between any two of the contact pads electrically connected to the corresponding first non-signal through vias.

Abstract: A plunger is suitable for a chip-testing module having a probe card, which has a circuit board and a membrane. The membrane has a circuit layer disposed on a first membrane surface of the membrane, conductive through-vias penetrating the membrane, and bumps disposed on a second membrane surface opposite to the first membrane surface, located in a pushed area of the membrane, and electrically connected to the circuit layer through the conductive through-vias. The plunger includes a body having a pushing part and a base part and a conductive layer disposed on a surface of the pushing part and the base part. Part of the circuit layer located in the pushed area is suitable for contacting and being electrically connected to part of the conductive layer located on the pushing part. The bumps are electrically connected to the conductive layer through the conductive through-vias.

Abstract: A chip structure includes a substrate with at least an arrangement of side pads on an active surface of the substrate and adjacent to one side of the active surface. The arrangement of side pads includes an outer pad row, a middle pad row and an inner pad row disposed along the extension direction of the side. The middle pad row is further away from the side than the outer pad row. The inner pad row is further away from the side than the middle pad row. Pads of the middle pad row and pads of the inner pad row are staggered. One non-signal pad of the middle pad row is located between two adjacent signal pads of the inner pad row, and one non-signal pad of the inner pad row is located between two adjacent signal pads of the middle pad row.

Abstract: A signal transmission structure suitable for a multi-layer circuit substrate comprising a core layer and at least a dielectric layer is provided. The signal transmission structure according to the present invention comprises a first via landing pad and a reference plane. The first via landing pad is disposed on a first surface of the core layer, and covering one end of the through hole of the core layer. The dielectric layer covers the first via landing pad and the first surface of the core layer. And the first reference plane is disposed above the dielectric layer, having a first opening disposed above one end of the through hole. Wherein, the area where the first reference plane is projected on the first surface of the core layer does not overlap with the area where the first via landing pad is projected on the first surface of the core layer.

Abstract: A testing assembly for an electrical test of an electronic package is provided. The testing assembly includes a testing circuit board and a testing socket mounted thereon. The testing socket includes an insulating body and a plurality of pins. The insulating body has a holding surface for supporting a contact surface of the electronic package, and at least one low-dielectric constant region located between two neighboring pins, and the dielectric constant of the low-electric constant region is lower than other regions of the insulating body. In addition, the pins passing through the insulating body are configured as the electric channels between a plurality of contacts on the contact surface and a plurality of testing pads on a conductive layer on a surface of the testing circuit board. Furthermore, the pins include a signal pin, and one end of the signal pin is electrically coupled to the signal testing pad.

Abstract: A plunger is suitable for a chip-testing module having a probe card, which has a circuit board and a membrane. The membrane has a circuit layer disposed on a first membrane surface of the membrane, conductive through-vias penetrating the membrane, and bumps disposed on a second membrane surface opposite to the first membrane surface, located in a pushed area of the membrane, and electrically connected to the circuit layer through the conductive through-vias. The plunger includes a body having a pushing part and a base part and a conductive layer disposed on a surface of the pushing part and the base part. Part of the circuit layer located in the pushed area is suitable for contacting and being electrically connected to part of the conductive layer located on the pushing part. The bumps are electrically connected to the conductive layer through the conductive through-vias.

Abstract: An arrangement of non-signal through vias suitable for a wiring board is provided. The wiring board has a contact surface, a core layer and pads. The contact pads are disposed on the contact surface, while the arrangement of non-signal through vias includes first non-signal through vias and a second non-signal through via. The first non-signal through vias pass through the core layer and are electrically connected to some of the contact pads. The second non-signal through via which passes through the core layer is disposed between the first non-signal through vias and is not electrically connected to the contact pads. The interval between the second non-signal through via and anyone of the surrounding first non-signal through vias is smaller than or equal to 0.72 times of the minimum interval between the second non-signal through via and one of the contact pads electrically connected to the corresponding first non-signal through vias.

Abstract: A wiring board including a plurality of patterned conductive layers and a plurality of insulating layers is provided. The patterned conductive layers include a first patterned conductive layer and at least one second patterned conductive layer. The first patterned conductive layer has at least one pair of differential signal lines and the second patterned conductive layer has at least one non-wiring area. A projection of the pair of differential signal lines on the second patterned conductive layer at least partially overlaps the non-wiring area. In addition, the insulating layers are disposed between the adjacent patterned conductive layers respectively.

Abstract: A lead arrangement applied to the leadframe of a chip package is provided. The lead arrangement includes at least a pair of differential signal leads and at least a non-differential signal lead. The pair of differential signal leads includes a first differential signal lead and a second differential signal lead. The non-differential signal lead is disposed between the first differential signal lead and the second differential signal lead.

Abstract: A testing assembly for an electrical test of an electronic package is provided. The testing assembly includes a testing circuit board and a testing socket mounted thereon. The testing socket includes an insulating body and a plurality of pins. The insulating body has a holding surface for supporting a contact surface of the electronic package, and at least one low-dielectric constant region located between two neighboring pins, and the dielectric constant of the low-electric constant region is lower than other regions of the insulating body. In addition, the pins passing through the insulating body are configured as the electric channels between a plurality of contacts on the contact surface and a plurality of testing pads on a conductive layer on a surface of the testing circuit board. Furthermore, the pins include a signal pin, and one end of the signal pin is electrically coupled to the signal testing pad.

Abstract: A chip structure includes a substrate with at least an arrangement of side pads on an active surface of the substrate and adjacent to one side of the active surface. The arrangement of side pads includes an outer pad row, a middle pad row and an inner pad row disposed along the extension direction of the side. The middle pad row is further away from the side than the outer pad row. The inner pad row is further away from the side than the middle pad row. Pads of the middle pad row and pads of the inner pad row are staggered. One non-signal pad of the middle pad row is located between two adjacent signal pads of the inner pad row, and one non-signal pad of the inner pad row is located between two adjacent signal pads of the middle pad row.