Abstract: A heterogeneous computing system performs data synchronization. The heterogeneous computing system includes a system memory, a cluster, and a processing unit outside the cluster. The cluster includes a sync circuit, inner processors, and a snoop filter. The sync circuit is operative to receive a sync command indicating a sync address range. The sync command is issued by one of the processing unit and the inner processors. The sync circuit further determines whether addresses recorded in the snoop filter fall within the sync address range. In response to a determination that a recorded address falls within the sync address range, the sync circuit notifies a target one of the inner processors that owns a cache line having the recorded address to take a sync action on the cache line.

Abstract: A memory control method includes a processor initiating a memory access instruction to a cache controller to search a cache memory, an address detector checking if the memory access instruction is corresponding to predetermined conditions if a cache miss occurs, the address detector transmitting a signal to inform a replacement mask logic unit if the memory access instruction is corresponding to the predetermined conditions, and the replacement mask logic unit providing predetermined data to store the predetermined data into the cache memory.

Abstract: A pipelined processor for carrying out pipeline processing of instructions, which undergo a plurality of stages, is provided. The pipelined processor includes: a memory-activation indicator and a memory controller. The memory-activation indicator stores content information that indicates whether to activate a first volatile memory and/or a second volatile memory while performing a current instruction. The memory controller is arranged for controlling activation of the first volatile memory and/or the second volatile memory in a specific stage of the plurality of stages of the current instruction according to the content information stored in the memory-activation indicator.

Abstract: A pipelined processor for carrying out pipeline processing of instructions, which undergo a plurality of stages, is provided. The pipelined processor includes: a memory-activation indicator and a memory controller. The memory-activation indicator stores content information that indicates whether to activate a first volatile memory and/or a second volatile memory while performing a current instruction. The memory controller is arranged for controlling activation of the first volatile memory and/or the second volatile memory in a specific stage of the plurality of stages of the current instruction according to the content information stored in the memory-activation indicator.

Abstract: A fault-tolerant system including a calculation unit and an output synthesizer is provided. The calculation unit receives a first environmental parameter and input data, wherein the calculation unit further includes a first and a second calculation circuits. The first calculation circuit is arranged to perform a calculation on the input data in response to the first environmental parameter to generate a first calculation result. The second calculation circuit is different from the first calculation circuit, and arranged to perform the calculation on the input data in response to the first environmental parameter to generate a second calculation result. The output synthesizer selects a first and a second set of bits from the first and the second calculation result according to a control signal, and synthesizes the first set of bits and the second set of bits in sequence to generate an adjusted calculation result.

Abstract: A fault-tolerant system including a calculation unit and an output synthesizer is provided. The calculation unit receives a first environmental parameter and input data, wherein the calculation unit further includes a first and a second calculation circuits. The first calculation circuit is arranged to perform a calculation on the input data in response to the first environmental parameter to generate a first calculation result. The second calculation circuit is different from the first calculation circuit, and arranged to perform the calculation on the input data in response to the first environmental parameter to generate a second calculation result. The output synthesizer selects a first and a second set of bits from the first and the second calculation result according to a control signal, and synthesizes the first set of bits and the second set of bits in sequence to generate an adjusted calculation result.

Abstract: A configurable common filterbank processor applicable for various audio standards and its processing method. Inverse modified discrete cosine transform (IMDCT) and window and overlap-add (WOA) decoding operations required by AC-3 and AAC, and IMDC, WOA, and matrixing decoding operations required by MP3 are divided into several different modes, and a quick algorithm is provided for expediting the operation of these modes, and a hardware architecture is designed universally for these modes, so that the hardware architecture can be applicable for the decoding operations of three different audio standards, respectively AC-3, AAC and MP3, to expand the scope of applicability of a decoder.

Abstract: A configurable common filterbank processor applicable for various audio standards and its processing method. Inverse modified discrete cosine transform (IMDCT) and window and overlap-add (WOA) decoding operations required by AC-3 and AAC, and IMDC, WOA, and matrixing decoding operations required by MP3 are divided into several different modes, and a quick algorithm is provided for expediting the operation of these modes, and a hardware architecture is designed universally for these modes, so that the hardware architecture can be applicable for the decoding operations of three different audio standards, respectively AC-3, AAC and MP3, to expand the scope of applicability of a decoder.