Abstract: The present disclosure provides to a semiconductor memory device. The semiconductor memory device includes a substrate having a cell area and a peripheral area; and a first bit line structure disposed on and protruding from a surface of the cell area. The first bit line structure is sandwiched by a pair of air gaps and a barrier layer is conformally overlaying the air gaps adjacent to the sidewalls of the first bit line structure and the cell area. The first bit line structure has a sidewall and an ascending top portion, and a landing pad is disposed over the ascending top portion and the sidewalls of the first bit line structure. The landing pad has an inclined surface corresponding to the ascending top portion of the first bit line structure.

Abstract: The present disclosure provides to a method for manufacturing a semiconductor memory device. The method includes receiving a substrate including a cell area and a peripheral area; forming a first bit line structure on a surface of the cell area; depositing a landing pad above the barrier layer and on the top surface of the first bit line structure; removing a top corner of the landing pad to form an inclined surface connecting a top surface of the landing pad to a sidewall of the landing pad; etching the nitride layer of the first bit line structure and the spacer nitride layer from the top opening so as to form a concavity; etching the spacer oxide layer from the concavity to form an air gap; and depositing a silicon nitride layer to seal the air gap.

Abstract: The present disclosure provides to a method for manufacturing a semiconductor memory device. The method includes receiving a substrate including a cell area and a peripheral area; forming a first bit line structure on a surface of the cell area; depositing a landing pad above the barrier layer and on the top surface of the first bit line structure; removing a top corner of the landing pad to form an inclined surface connecting a top surface of the landing pad to a sidewall of the landing pad; etching the nitride layer of the first bit line structure and the spacer nitride layer from the top opening so as to form a concavity; etching the spacer oxide layer from the concavity to form an air gap; and depositing a silicon nitride layer to seal the air gap.

Abstract: The present disclosure provides to a semiconductor memory device. The semiconductor memory device includes a substrate having a cell area and a peripheral area; and a first bit line structure disposed on and protruding from a surface of the cell area. The first bit line structure is sandwiched by a pair of air gaps and a barrier layer is conformally overlaying the air gaps adjacent to the sidewalls of the first bit line structure and the cell area. The first bit line structure has a sidewall and an ascending top portion, and a landing pad is disposed over the ascending top portion and the sidewalls of the first bit line structure. The landing pad has an inclined surface corresponding to the ascending top portion of the first bit line structure.