Abstract: A semiconductor memory structure includes a semiconductor substrate having an active region and an isolation region surrounding the active region; a cap layer disposed on the semiconductor substrate; and a plurality of bit lines disposed on the semiconductor substrate. Each of bit lines includes a first conductive pattern disposed on the semiconductor substrate; a second conductive pattern disposed on the first conductive pattern; and a dielectric pattern disposed on the second conductive pattern. A sidewall of the first conductive pattern is retracted from a sidewall of the second conductive pattern.

Abstract: A semiconductor structure including the following components is provided. Stack structures are located on a substrate and separated from each other. Isolation layers are located on the sidewalls of the stack structures. A contact is located on the substrate between two adjacent isolation layers. A landing pad is located on the contact. The landing pad is located on one of the two adjacent isolation layers. There is an opening on one side of the landing pad. A first dielectric layer is located in the opening. A porous dielectric layer is located between the first dielectric layer and the landing pad. The top surface of the porous dielectric layer is lower than the top surface of the landing pad and the top surface of the first dielectric layer to form a recess between the landing pad and the first dielectric layer. The recess exposes the sidewall of the landing pad.

Abstract: A method for forming a semiconductor memory structure includes providing a semiconductor substrate; forming a hard mask layer on the semiconductor substrate; forming a contact opening corresponding to the pair of word lines through the hard mask layer and a portion of the semiconductor substrate; forming a pair of spacers on sidewalls of the contact opening; filling the contact opening with a conductive material to form a contact; forming a bit line directly above the contact and the pair of spacers, and forming a dielectric liner on sidewalls of the bit line. The pair of word lines is embedded in an active region of the semiconductor substrate and extends in a first direction. The bit line extends in a second direction. The first direction is perpendicular to the second direction.

Abstract: Provided is a memory device including a substrate, a plurality of bit-line structures, a plurality of bit-line contacts, and a plurality of protective structures. The substrate has a plurality of active areas. The plurality of bit-line structures are disposed on the substrate in parallel along a X direction. The plurality of bit-line contacts are respectively disposed at overlaps of the plurality of bit-line structures and the plurality of active areas, and electrically connect the plurality of bit-line structures and the plurality of active areas. The plurality of protective structures are disposed at least on a first sidewall and a second sidewall of the plurality of bit-line contacts. A method of forming a memory device is also provided.

Abstract: A method for forming a semiconductor memory structure includes providing a semiconductor substrate; forming a hard mask layer on the semiconductor substrate; forming a contact opening corresponding to the pair of word lines through the hard mask layer and a portion of the semiconductor substrate; forming a pair of spacers on sidewalls of the contact opening; filling the contact opening with a conductive material to form a contact; forming a bit line directly above the contact and the pair of spacers, and forming a dielectric liner on sidewalls of the bit line. The pair of word lines is embedded in an active region of the semiconductor substrate and extends in a first direction. The bit line extends in a second direction. The first direction is perpendicular to the second direction.

Abstract: A housing includes a base and a mark piece. The base includes a bottom wall and at least one side wall. The at least one side wall is vertically connected to the bottom wall. A height of the side wall exists between a top end of the at least one side wall and the bottom wall. The mark piece is disposed on the bottom wall and extends from the bottom wall in a direction away from the bottom wall. The mark piece has a low scale and a high scale. A distance from the low scale to the bottom wall is less than the height of the side wall. A distance from the high scale to the bottom wall is substantially the same as the height of the side wall.

Abstract: A housing includes a base and a mark piece. The base includes a bottom wall and at least one side wall. The at least one side wall is vertically connected to the bottom wall. A height of the side wall exists between a top end of the at least one side wall and the bottom wall. The mark piece is disposed on the bottom wall and extends from the bottom wall in a direction away from the bottom wall. The mark piece has a low scale and a high scale. A distance from the low scale to the bottom wall is less than the height of the side wall. A distance from the high scale to the bottom wall is substantially the same as the height of the side wall.