Abstract: A semiconductor package includes a base comprising a top surface and a bottom surface that is opposite to the top surface; a first semiconductor chip mounted on the top surface of the base in a flip-chip manner; a second semiconductor chip stacked on the first semiconductor chip and electrically coupled to the base by wire bonding; an in-package heat dissipating element comprising a dummy silicon die adhered onto the second semiconductor chip by using a high-thermal conductive die attach film; and a molding compound encapsulating the first semiconductor die, the second semiconductor die, and the in-package heat dissipating element.

Abstract: A supported metallocene catalyst includes a carrier and a metallocene component. The carrier includes an inorganic oxide particle and an alkyl aluminoxane material. The inorganic oxide particle includes at least one inorganic oxide compound selected from the group consisting of an oxide of Group 3A and an oxide of Group 4A. The alkyl aluminoxane material includes an alkyl aluminoxane compound and an alkyl aluminum compound that is present in amount ranging from greater than 0.01 wt % to less than 14 wt % base on 100 wt % of the alkyl aluminoxane material. The metallocene component is supported on the carrier, and includes one of a metallocene compound containing a metal from Group 3B, a metallocene compound containing a metal from Group 4B, and a combination thereof. A method for preparing the supported metallocene catalyst and a method for preparing polyolefin using the supported metallocene catalyst are also disclosed.

Abstract: A method for forming a semiconductor memory structure includes providing a semiconductor substrate; forming a hard mask layer on the semiconductor substrate; forming a contact opening corresponding to the pair of word lines through the hard mask layer and a portion of the semiconductor substrate; forming a pair of spacers on sidewalls of the contact opening; filling the contact opening with a conductive material to form a contact; forming a bit line directly above the contact and the pair of spacers, and forming a dielectric liner on sidewalls of the bit line. The pair of word lines is embedded in an active region of the semiconductor substrate and extends in a first direction. The bit line extends in a second direction. The first direction is perpendicular to the second direction.

Abstract: According to an example, a device housing may have a support structure to hold a removably mounted computing component. The support structure may comprise a first rotatably mounted arm comprising a first post and a resilient biasing element attached to the arm. The resilient biasing element may bias the first arm in a direction towards engagement with the computing component such that the first post such that the first post holds the computing component in place.

Abstract: Provided is a memory device including a substrate, a plurality of bit-line structures, a plurality of bit-line contacts, and a plurality of protective structures. The substrate has a plurality of active areas. The plurality of bit-line structures are disposed on the substrate in parallel along a X direction. The plurality of bit-line contacts are respectively disposed at overlaps of the plurality of bit-line structures and the plurality of active areas, and electrically connect the plurality of bit-line structures and the plurality of active areas. The plurality of protective structures are disposed at least on a first sidewall and a second sidewall of the plurality of bit-line contacts. A method of forming a memory device is also provided.

Abstract: A method for forming a semiconductor memory structure includes providing a semiconductor substrate; forming a hard mask layer on the semiconductor substrate; forming a contact opening corresponding to the pair of word lines through the hard mask layer and a portion of the semiconductor substrate; forming a pair of spacers on sidewalls of the contact opening; filling the contact opening with a conductive material to form a contact; forming a bit line directly above the contact and the pair of spacers, and forming a dielectric liner on sidewalls of the bit line. The pair of word lines is embedded in an active region of the semiconductor substrate and extends in a first direction. The bit line extends in a second direction. The first direction is perpendicular to the second direction.

Abstract: A housing includes a base and a mark piece. The base includes a bottom wall and at least one side wall. The at least one side wall is vertically connected to the bottom wall. A height of the side wall exists between a top end of the at least one side wall and the bottom wall. The mark piece is disposed on the bottom wall and extends from the bottom wall in a direction away from the bottom wall. The mark piece has a low scale and a high scale. A distance from the low scale to the bottom wall is less than the height of the side wall. A distance from the high scale to the bottom wall is substantially the same as the height of the side wall.

Abstract: A housing includes a base and a mark piece. The base includes a bottom wall and at least one side wall. The at least one side wall is vertically connected to the bottom wall. A height of the side wall exists between a top end of the at least one side wall and the bottom wall. The mark piece is disposed on the bottom wall and extends from the bottom wall in a direction away from the bottom wall. The mark piece has a low scale and a high scale. A distance from the low scale to the bottom wall is less than the height of the side wall. A distance from the high scale to the bottom wall is substantially the same as the height of the side wall.