Patents by Inventor Hsing Huang
Hsing Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12366595Abstract: A voltage monitoring system includes a voltage dividing circuit and a voltage monitoring device. The voltage dividing circuit is configured to divide a power signal to generate an input voltage. The voltage monitoring device includes an input node, a shunt circuit, a first detection circuit and a second detection circuit. The input node receives the input voltage. The shunt circuit is configured to compare the input voltage with a voltage threshold value to selectively operate in a conducted state or a switched-off state, and configured to output a flag signal to indicate the conducted state or the switched-off state of the shunt circuit. The first detection circuit generates a first detection signal corresponding to the input voltage. The second detection circuit generates a second detection signal corresponding to the power signal according to the flag signal and the first detection signal.Type: GrantFiled: October 20, 2022Date of Patent: July 22, 2025Assignee: Realtek Semiconductor CorporationInventors: Yueh-Hsing Huang, Li-Chen Liu, Chun-Hsi Huang
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Publication number: 20250209034Abstract: An information transceiving method, applied to an information transceiving system with a transmission device and a reception device, the transmission device comprising a first TX input interface following a first transceiving specification and a second TX input interface following a second transceiving specification, the reception device comprising a first RX output interface following a third transceiving specification.Type: ApplicationFiled: December 20, 2024Publication date: June 26, 2025Applicant: Realtek Semiconductor Corp.Inventor: Yueh-Hsing Huang
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Patent number: 12328659Abstract: A mesh network system and a mesh network resource allocation method are provided. The mesh network system includes a first router having a processor. The processor is used to detect a network architecture, according to the network architecture, designate a role of a second router as a transmitting device or a receiving device, and assign a work to the second router base on the role. After receiving the work assignment, the second router processes an event of the work and continuously monitors an activity related to the work.Type: GrantFiled: April 18, 2022Date of Patent: June 10, 2025Assignee: WISTRON NEWEB CORP.Inventors: Chui-Chu Cheng, Wang-Hsing Huang, Yi-An Chen, Tsung-Yu Ho
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Publication number: 20250174966Abstract: Provided is a vertical cavity surface emitting laser diode (VCSEL). A tunnel junction with a high doping concentration is provided in the VCSEL. An n-type semiconductor layer of the tunnel junction has stress relative to the substrate, and is doped with at least one element such that the tunnel junction not only has a high doping concentration, but also the epitaxial layer can be oxidized and the oxidation rate is relatively stable during the oxidation process. Alternatively, the n-type semiconductor layer is doped with at least two elements. As a result, the oxidation process of the VCSEL can be stably performed, and the resistance of the tunnel junction with a high doping concentration is low. The tunnel junction is suitable to be arranged between two active layers of the VCSEL or between the p-type semiconductor and the n-type semiconductor layer of the VCSEL.Type: ApplicationFiled: January 16, 2025Publication date: May 29, 2025Applicant: VISUAL PHOTONICS EPITAXY CO., LTD.Inventors: Chao-Hsing Huang, Yu-Chung Chin, Van-Truong Dai
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Patent number: 12295152Abstract: Provided is a high ruggedness heterojunction bipolar transistor (HBT), including a substrate, a sub-collector layer, collector layer, a base layer, and an emitter layer. The collector layer includes a InGaP layer or a wide bandgap layer. The collector layer includes III-V semiconductor material. The bandgap of the wide bandgap layer is greater than that of GaAs.Type: GrantFiled: February 10, 2024Date of Patent: May 6, 2025Assignee: VISUAL PHOTONICS EPITAXY CO., LTD.Inventors: Chao-Hsing Huang, Yu-Chung Chin, Kai-Yu Chen
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Patent number: 12250519Abstract: A MEMS capacitance microphone includes a substrate, a diaphragm, a back plate structure and a plurality of support structures. The substrate is provided with a plurality of gate structures and a cavity penetrating through the substrate, and the gate structures extend from an inner wall of the cavity to the center of the cavity. The diaphragm is vibratably arranged on one side of the substrate and includes a main deformation zone and a non-main deformation zone. The back plate structure is arranged on the diaphragm, and the diaphragm is located between the substrate and the back plate structure. The support structures are arranged on the back plate structure, penetrate the periphery of the main deformation zone, and respectively abut against the gate structures. The MEMS capacitance microphone has higher rigidity of a back plate, and is capable of greatly reducing the impedance of air to increase its signal-to-noise ratio.Type: GrantFiled: August 24, 2022Date of Patent: March 11, 2025Assignee: Qsensing Microelectronics Co., LtdInventor: Chien-Hsing Huang
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Publication number: 20250055257Abstract: A vertical cavity surface emitting laser diode (VCSEL) includes a substrate, a lower Bragg reflector (DBR) layer, an active region, an upper Bragg reflector (DBR) layer, and a current confinement layer. The lower DBR layer is on the substrate. The active region is on the lower DBR layer on the active region. The current confinement layer is inside or outside the active region. When the current confinement layer comprises a compound containing phosphorus, such as AlAsP or AlGaAsP, and the phosphorus (P) content is within a specific range, the insulation rate of the current confinement layer will not be excessively fast to the point of being difficult to control. Additionally, the reproducibility of the aperture in the current confinement layer between batches of the VCSEL production is improved. Furthermore, the divergence angle of the VCSEL can be further reduced, thereby significantly enhancing the sensing capabilities of Lidar or 3D sensing.Type: ApplicationFiled: October 28, 2024Publication date: February 13, 2025Applicant: VISUAL PHOTONICS EPITAXY CO., LTD.Inventors: Van-Truong Dai, Van-Chien Nguyen, Yu-Chung Chin, Chao-Hsing Huang
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Publication number: 20240222477Abstract: Provided is a high ruggedness heterojunction bipolar transistor (HBT), including a substrate, a sub-collector layer, collector layer, a base layer, and an emitter layer. The collector layer includes a InGaP layer or a wide bandgap layer. The collector layer includes III-V semiconductor material. The bandgap of the wide bandgap layer is greater than that of GaAs.Type: ApplicationFiled: February 10, 2024Publication date: July 4, 2024Inventors: Chao-Hsing HUANG, Yu-Chung CHIN, Kai-Yu CHEN
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Patent number: 11972720Abstract: A method for matching parameters applied to a display device and a circuit system that performs the method are provided. In the method, when a display device is activated, a circuit system connects to a panel module of the display device for retrieving parameters from a panel memory. The parameters are such as video display parameters, camera image parameters, speaker audio parameters, and microphone receiving parameters. After the parameters are applied to the circuit system, the circuit system operates the display device using the parameters. The data generated by the circuit system can be adjusted for matching new parameters. Afterwards, when the new parameters are applied to the circuit system, video and audio are outputted according to the matched parameters, and the camera and microphone in the panel module are also operated according to the matched parameters.Type: GrantFiled: May 4, 2022Date of Patent: April 30, 2024Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Yueh-Hsing Huang, Sen-Huang Tang, Wu-Chih Lin, Yen-Hsing Wu
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Patent number: 11929427Abstract: Provided is a high ruggedness heterojunction bipolar transistor (HBT), including a collector layer. The collector layer includes a InGaP layer or a wide bandgap layer. The bandgap of the InGaP layer is greater than 1.86 eV.Type: GrantFiled: January 14, 2021Date of Patent: March 12, 2024Assignee: VISUAL PHOTONICS EPITAXY CO., LTD.Inventors: Chao-Hsing Huang, Yu-Chung Chin, Kai-Yu Chen
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Publication number: 20240079510Abstract: The present invention is a semiconductor device having a defect blocking region. The semiconductor device includes a substrate, a defect source region, a semiconductor layer and a defect blocking region. The defect source region is on the substrate, wherein the defect source region is a metamorphic buffer layer or a buffer layer, the semiconductor layer over the defect source region, wherein a lattice constant of the semiconductor layer is different from a lattice constant of the substrate. The defect blocking region is disposed on the substrate and below the semiconductor layer, wherein the defect blocking region includes a superlattice structure, wherein at least one of two adjacent layers of the superlattice structure has strain relative to the semiconductor layer, or a lattice constant of the superlattice structure is close to or equal to the lattice constant of the semiconductor layer.Type: ApplicationFiled: May 5, 2023Publication date: March 7, 2024Applicant: VISUAL PHOTONICS EPITAXY CO., LTD.Inventors: Van-Truong DAI, Yu-Chung CHIN, Chao-Hsing HUANG
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Publication number: 20240079450Abstract: A heterojunction bipolar transistor structure is provided, including a substrate and a multi-layer structure formed on the substrate. The multi-layer structure includes a current clamping layer, and the current clamping layer can be disposed in a collector layer, disposed in a sub-collector layer, or interposed between a collector layer and a sub-collector layer. An electron affinity of the current clamping layer is less than an electron affinity of an epitaxial layer formed on the current clamping layer.Type: ApplicationFiled: August 31, 2023Publication date: March 7, 2024Inventors: Yu-Chung CHIN, Zong-Lin LI, Chao-Hsing HUANG
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Publication number: 20240030685Abstract: A semiconductor laser diode includes a substrate; a lower epitaxial region located on the substrate, wherein the lower epitaxial region includes a lower DBR layer; an active region located on the lower epitaxial region; and an upper epitaxial region located on the substrate, wherein the upper epitaxial region includes a lower DBR layer; wherein the lower DBR layer includes a P-type lower DBR region and the upper DBR layer includes an N-type upper DBR region.Type: ApplicationFiled: July 19, 2023Publication date: January 25, 2024Inventors: Van-Truong DAI, Yu-Chung CHIN, Chao-Hsing HUANG
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Patent number: 11869816Abstract: A package substrate comprises first, second and third electrical test contacts, wherein the package substrate is provided with an upper element plane and a lower SMD electrode plane on two sides. The side edge of the upper element plane is provided with first and second electrodes of the main element and first and second electrodes of the secondary element. The main element of LED chip is electrically connected between the first and second electrodes of the main element, a parallel circuit secondary element is electrically connected between the first and second electrodes of the secondary element. The electrical characteristics of the main element of LED chip and the parallel circuit secondary element are measured through the first, second, and third electrical test contacts when electrically connected.Type: GrantFiled: July 26, 2021Date of Patent: January 9, 2024Assignee: EXCELLENCE OPTO. INC.Inventors: Fu-Bang Chen, Chih-Chiang Chang, Chang-Ching Huang, Chun-Ming Lai, Wen-Hsing Huang, Tzeng-Guang Tsai, Kuo-Hsin Huang
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Patent number: 11869817Abstract: The invention comprises a light emitting diode chip and a package substrate. The light emitting diode chip is provided with a semiconductor epitaxial structure, a lateral extending interface structure, a chip conductive structure, an N-type electrode located above the semiconductor epitaxial structure and a P-type bypass detection electrode located on the lateral extending interface structure. The chip conductive structure is provided with a P-type main electrode located on a lower side. The package substrate comprises a plurality of electrode contacts through which the N-type electrode, the P-type bypass detection electrode and the P-type main electrode are connected, and a process quality of a alternative substrate adhesive layer in one of the semiconductor epitaxial structure and the chip conductive structure and a chip-substrate bonding adhesive layer between the P-type main electrode and the package substrate is evaluated by detecting electrical characteristics.Type: GrantFiled: July 26, 2021Date of Patent: January 9, 2024Assignee: EXCELLENCE OPTO. INC.Inventors: Fu-Bang Chen, Chih-Chiang Chang, Chang-Ching Huang, Chun-Ming Lai, Wen-Hsing Huang, Tzeng-Guang Tsai, Kuo-Hsin Huang
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Patent number: 11862938Abstract: Provided is a semiconductor laser diode, including a GaAs/In P substrate and a multi-layer structure on the GaAs/InP substrate. The multi-layer structure includes a lower epitaxial region, an active region and an upper epitaxial region. The active region comprises a first active layer, an epitaxial region and a second active layer, the epitaxial region is disposed between the first active layer and the second active layer, the first active layer comprises one or more quantum well structures or one or more quantum dot structures, and the second active layer comprises one or more quantum well structures or one or more quantum dot structures.Type: GrantFiled: June 11, 2020Date of Patent: January 2, 2024Assignee: VISUAL PHOTONICS EPITAXY CO., LTD.Inventors: Chao-Hsing Huang, Yu-Chung Chin, Van-Truong Dai, Jhao-Hang He, Hung-Chi Hsiao
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Patent number: 11846659Abstract: A power capability determination device is arranged to determine a power capability of a power source, and includes a connector, a load circuit, a switch circuit, a voltage monitor circuit, and a processing circuit. The connector is arranged to receive the power source to output an input voltage at a power output terminal. The switch circuit is electrically connected between the load circuit and the power output terminal. The voltage monitor circuit is electrically connected to the power output terminal, and is arranged to monitor the input voltage to generate a monitored voltage value. The processing circuit is electrically connected to the voltage monitor circuit and the switch circuit, and is arranged to control the switch circuit, and in a state of controlling the switch circuit, receive the monitored voltage value and determine the power capability of the power source according to the monitored voltage value.Type: GrantFiled: May 13, 2022Date of Patent: December 19, 2023Assignee: Realtek Semiconductor Corp.Inventors: Yueh-Hsing Huang, Sen-Huang Tang
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Publication number: 20230403514Abstract: A MEMS capacitance microphone includes a substrate, a diaphragm, a back plate structure and a plurality of support structures. The substrate is provided with a plurality of gate structures and a cavity penetrating through the substrate, and the gate structures extend from an inner wall of the cavity to the center of the cavity. The diaphragm is vibratably arranged on one side of the substrate and includes a main deformation zone and a non-main deformation zone. The back plate structure is arranged on the diaphragm, and the diaphragm is located between the substrate and the back plate structure. The support structures are arranged on the back plate structure, penetrate the periphery of the main deformation zone, and respectively abut against the gate structures. The MEMS capacitance microphone has higher rigidity of a back plate, and is capable of greatly reducing the impedance of air to increase its signal-to-noise ratio.Type: ApplicationFiled: August 24, 2022Publication date: December 14, 2023Inventor: Chien-Hsing Huang
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Patent number: D1027868Type: GrantFiled: December 23, 2020Date of Patent: May 21, 2024Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: An-Ming Lee, Bo-Kai Huang, Wu-Chih Lin, Yueh-Hsing Huang
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Patent number: D1032537Type: GrantFiled: December 23, 2020Date of Patent: June 25, 2024Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: An-Ming Lee, Bo-Kai Huang, Wu-Chih Lin, Yueh-Hsing Huang