Abstract: A method to generate control signals for a display-panel driver, which needs to receive a set of predetermined number of input signals so as to output a set of control signals. The method includes starting with a reset process. The display-panel driver receives a first part of the set of input signals through multiple input terminals. At least two of the input terminals are used as secondary input terminals, and at least two enabling input signals of different definitions are input, respectively. The enabling input signals internally enable a control signal generator to generate a second part of the set of input signals. The second part of the set of input signals and the first part of the set of input signals form a complete set of input signals. When a serial data of the input signals cannot satisfy the predetermined format, the method goes back to the reset process.

Abstract: A method to generate control signals for a display-panel driver, which needs to receive a set of predetermined number of input signals so as to output a set of control signals. The method includes starting with a reset process. The display-panel driver receives a first part of the set of input signals through multiple input terminals. At least two of the input terminals are used as secondary input terminals, and at least two enabling input signals of different definitions are input, respectively. The enabling input signals internally enable a control signal generator to generate a second part of the set of input signals. The second part of the set of input signals and the first part of the set of input signals form a complete set of input signals. When a serial data of the input signals cannot satisfy the predetermined format, the method goes back to the reset process.

Abstract: An LCD device includes an LCD panel, a timing controller, a plurality of gate drivers, and a plurality of source drivers. The timing controller generates a plurality of horizontal synchronization signals respectively corresponding to the plurality of source drivers based on the signal transmission paths between the plurality of source drivers and the timing controller. The timing controller generates a plurality of vertical synchronization signals respectively corresponding to the plurality of gate drivers based on the signal transmission paths between the plurality of gate drivers and the timing controller. Each source driver outputs a source driving signal based on a horizontal clock signal, a data signal, a horizontal control signal, and a corresponding horizontal synchronization signal. Each gate driver outputs a gate driving signal based on a vertical clock signal, a vertical control signal, and a corresponding vertical synchronization signal.