Patents by Inventor Hsing-Jui Lee
Hsing-Jui Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10858736Abstract: An atomic layer deposition apparatus includes a chamber including a plurality of regions; and a heating device respectively providing specific temperature ranges for the plurality of regions. By flowing precursor gases at different flow rates in the different regions, thin films can be simultaneously formed in the different regions having different film thicknesses.Type: GrantFiled: December 6, 2016Date of Patent: December 8, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Yi Chuang, Hsing-Jui Lee, Ming-Te Chen
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Patent number: 10049856Abstract: A method includes providing a semiconductor substrate, and performing an ion implantation process to a surface of the substrate. The ion implantation process includes intermittently applying an ion beam to the surface, and while applying the ion beam, applying a heating process with a heating temperature above a threshold level.Type: GrantFiled: May 16, 2016Date of Patent: August 14, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsin-Wei Wu, Chun-Feng Nieh, Yu Chi-Fu, Hsing-Jui Lee, Tsun-Jen Chan
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Publication number: 20170081761Abstract: An atomic layer deposition apparatus includes a chamber including a plurality of regions; and a heating device respectively providing specific temperature ranges for the plurality of regions. By flowing precursor gases at different flow rates in the different regions, thin films can be simultaneously formed in the different regions having different film thicknesses.Type: ApplicationFiled: December 6, 2016Publication date: March 23, 2017Inventors: Chia-Yi Chuang, Hsing-Jui Lee, Ming-Te Chen
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Patent number: 9512519Abstract: An atomic layer deposition apparatus includes a chamber including a plurality of regions; and a heating device respectively providing specific temperature ranges for the plurality of regions.Type: GrantFiled: December 3, 2012Date of Patent: December 6, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Yi Chuang, Hsing-Jui Lee, Ming-Te Chen
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Publication number: 20160260580Abstract: A method includes providing a semiconductor substrate, and performing an ion implantation process to a surface of the substrate. The ion implantation process includes intermittently applying an ion beam to the surface, and while applying the ion beam, applying a heating process with a heating temperature above a threshold level.Type: ApplicationFiled: May 16, 2016Publication date: September 8, 2016Inventors: Hsin-Wei Wu, Chun-Feng Nieh, Yu Chi-Fu, Hsing-Jui Lee
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Patent number: 9343312Abstract: A method includes providing a semiconductor substrate, and performing an ion implantation process to a surface of the substrate. The ion implantation process includes intermittently applying an ion beam to the surface, and while applying the ion beam, applying a heating process with a heating temperature above a threshold level.Type: GrantFiled: July 25, 2014Date of Patent: May 17, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsin-Wei Wu, Tsun-Jen Chan, Chun-Feng Nieh, Hsing-Jui Lee, Yu-Chi Fu
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Publication number: 20160027646Abstract: A method includes providing a semiconductor substrate, and performing an ion implantation process to a surface of the substrate. The ion implantation process includes intermittently applying an ion beam to the surface, and while applying the ion beam, applying a heating process with a heating temperature above a threshold level.Type: ApplicationFiled: July 25, 2014Publication date: January 28, 2016Inventors: Hsin-Wei Wu, Tsun-Jen Chan, Chun-Feng Nieh, Hsing-Jui Lee, Yu-Chi Fu
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Patent number: 9209243Abstract: Embodiments of the disclosure include a shallow trench isolation (STI) structure and a method of forming the same. A trench is formed in a substrate. A silicon oxide and a silicon liner layer are formed on sidewalls and a bottom surface of the trench. A flowable silicon oxide material fills in the trench, is cured, and then is partially removed. Another silicon oxide is deposited in the trench to fill the trench. The STI structure in a fabricated device includes a bottom portion having silicon oxide and a top portion having additionally a silicon oxide liner and a silicon liner on the sidewalls.Type: GrantFiled: February 12, 2015Date of Patent: December 8, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Yi Chuang, Ta-Hsiang Kung, Hsing-Jui Lee, Ming-Te Chen
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Publication number: 20150155352Abstract: Embodiments of the disclosure include a shallow trench isolation (STI) structure and a method of forming the same. A trench is formed in a substrate. A silicon oxide and a silicon liner layer are formed on sidewalls and a bottom surface of the trench. A flowable silicon oxide material fills in the trench, is cured, and then is partially removed. Another silicon oxide is deposited in the trench to fill the trench. The STI structure in a fabricated device includes a bottom portion having silicon oxide and a top portion having additionally a silicon oxide liner and a silicon liner on the sidewalls.Type: ApplicationFiled: February 12, 2015Publication date: June 4, 2015Inventors: Chia-Yi Chuang, Ta-Hsiang Kung, Hsing-Jui Lee, Ming-Te Chen
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Patent number: 8975155Abstract: Embodiments of the disclosure include a shallow trench isolation (STI) structure and a method of forming the same. A trench is formed in a substrate. A silicon oxide and a silicon liner layer are formed on sidewalls and a bottom surface of the trench. A flowable silicon oxide material fills in the trench, is cured, and then is partially removed. Another silicon oxide is deposited in the trench to fill the trench. The STI structure in a fabricated device includes a bottom portion having silicon oxide and a top portion having additionally a silicon oxide liner and a silicon liner on the sidewalls.Type: GrantFiled: July 10, 2013Date of Patent: March 10, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Yi Chuang, Ta-Hsiang Kung, Hsing-Jui Lee, Ming-Te Chen
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Publication number: 20150014807Abstract: Embodiments of the disclosure include a shallow trench isolation (STI) structure and a method of forming the same. A trench is formed in a substrate. A silicon oxide and a silicon liner layer are formed on sidewalls and a bottom surface of the trench. A flowable silicon oxide material fills in the trench, is cured, and then is partially removed. Another silicon oxide is deposited in the trench to fill the trench. The STI structure in a fabricated device includes a bottom portion having silicon oxide and a top portion having additionally a silicon oxide liner and a silicon liner on the sidewalls.Type: ApplicationFiled: July 10, 2013Publication date: January 15, 2015Inventors: Chia-Yi Chuang, Ta-Hsiang Kung, Hsing-Jui Lee, Ming-Te Chen
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Publication number: 20140154414Abstract: An atomic layer deposition apparatus includes a chamber including a plurality of regions; and a heating device respectively providing specific temperature ranges for the plurality of regions.Type: ApplicationFiled: December 3, 2012Publication date: June 5, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Yi CHUANG, Hsing-Jui Lee, Ming-Te Chen
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Publication number: 20140038421Abstract: A system and method are disclosed for processing semiconductors. An embodiment comprises a reaction chamber for processing wafers and having walls tapering at an angle that is greater than 0 degrees and less than about 35 degrees from a first end optionally having a diameter of 341 to 380 millimeters to a second end optionally having a diameter of 300 to 340 millimeters at a second end, with gas flow from the first end to the second end, and having at least one deposition injector near the first end of the reaction chamber and having a plurality of injector openings that disperse injection material across a cross section of the reaction chamber for forming a deposition layer.Type: ApplicationFiled: August 1, 2012Publication date: February 6, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kai-Lun Kuo, Ming-Te Chen, Hsing-Jui Lee, Yu-Yen Lin, Yen-Chen Lin
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Patent number: 8222132Abstract: The present disclosure provides a method that includes forming first and second gate structures over first and second regions, respectively, removing a first dummy gate and first dummy dielectric from the first gate structure thereby forming a first trench and removing a second dummy gate and second dummy dielectric from the second gate structure thereby forming a second trench, forming a gate layer to partially fill the first and second trenches, forming a material layer to fill the remainder of the first and second trenches, removing a portion of the material layer such that a remaining portion of the material layer protects a first portion of the gate layer located at a bottom portion of the first and second trenches, removing a second portion of the gate layer, removing the remaining portion of the material layer from the first and second trenches.Type: GrantFiled: September 25, 2009Date of Patent: July 17, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Da-Yuan Lee, Jian-Hao Chen, Chi-Chun Chen, Matt Yeh, Hsing-Jui Lee
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Publication number: 20100124818Abstract: The present disclosure provides a method that includes forming first and second gate structures over first and second regions, respectively, removing a first dummy gate and first dummy dielectric from the first gate structure thereby forming a first trench and removing a second dummy gate and second dummy dielectric from the second gate structure thereby forming a second trench, forming a gate layer to partially fill the first and second trenches, forming a material layer to fill the remainder of the first and second trenches, removing a portion of the material layer such that a remaining portion of the material layer protects a first portion of the gate layer located at a bottom portion of the first and second trenches, removing a second portion of the gate layer, removing the remaining portion of the material layer from the first and second trenches.Type: ApplicationFiled: September 25, 2009Publication date: May 20, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Da-Yuan Lee, Jian-Hao Chen, Chi-Chun Chen, Matt Yeh, Hsing-Jui Lee
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Publication number: 20050124169Abstract: A truncated dummy plate which is suitable for promoting substantially uniform flow of process gases among all regions on the surface of a substrate to facilitate deposition of a film having uniform thickness on the substrate. The truncated dummy plate has a circular shape with a flat edge provided in the curved edge of the dummy plate. At least two, and preferably, about three or four of the dummy plates are positioned in the sites on a wafer boat which are in relatively close proximity to a gas outlet in a process furnace typically during a LPCVD process carried out in the furnace. The flat or truncated edges of the dummy plates are disposed on the gas inlet side of the process chamber, with the round edges of the dummy plates disposed on the gas outlet side of the process chamber.Type: ApplicationFiled: January 19, 2005Publication date: June 9, 2005Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yen-Hsing Chen, Hsing-Jui Lee, Fu-Kuo Tseng, Ching-Ling Lee, Kuo-Hung Liao
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Patent number: 6849131Abstract: A truncated dummy plate which is suitable for promoting substantially uniform flow of process gases among all regions on the surface of a substrate to facilitate deposition of a film having uniform thickness on the substrate. The truncated dummy plate has a circular shape with a flat edge provided in the curved edge of the dummy plate. At least two, and preferably, about three or four of the dummy plates are positioned in the sites on a wafer boat which are in relatively close proximity to a gas outlet in a process furnace typically during a LPCVD process carried out in the furnace. The flat or truncated edges of the dummy plates are disposed on the gas inlet side of the process chamber, with the round edges of the dummy plates disposed on the gas outlet side of the process chamber.Type: GrantFiled: October 5, 2002Date of Patent: February 1, 2005Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Yen-Hsing Chen, Hsing-Jui Lee, Fu-Kuo Tseng, Ching-Ling Lee, Kuo-Hung Liao
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Publication number: 20040065261Abstract: A truncated dummy plate which is suitable for promoting substantially uniform flow of process gases among all regions on the surface of a substrate to facilitate deposition of a film having uniform thickness on the substrate. The truncated dummy plate has a circular shape with a flat edge provided in the curved edge of the dummy plate. At least two, and preferably, about three or four of the dummy plates are positioned in the sites on a wafer boat which are in relatively close proximity to a gas outlet in a process furnace typically during a LPCVD process carried out in the furnace. The flat or truncated edges of the dummy plates are disposed on the gas inlet side of the process chamber, with the round edges of the dummy plates disposed on the gas outlet side of the process chamber.Type: ApplicationFiled: October 5, 2002Publication date: April 8, 2004Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yen-Hsing Chen, Hsing-Jui Lee, Fu-Kuo Tseng, Ching-Ling Lee, Kuo-Hung Liao
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Publication number: 20030160179Abstract: A method for reducing a dinitrogen (N2) ion concentration in an ion implanter including providing an ion implanter having an ion source chamber for producing source ions said ion source chamber surrounded by a plurality of source magnets having a current supply for altering a position of said source ions; providing a gaseous source of material to the ion source chamber for ionization thereby creating a supply of source ions for implantation; creating a supply of source ions to include dinitrogen (N2) ions and nitrogen (N) ions supplied for implantation; and, increasing a current supply to at least one of the plurality of source magnets such that a ratio of dinitrogen (N2) ions to nitrogen (N) ions supplied for implantation is reduced.Type: ApplicationFiled: February 22, 2002Publication date: August 28, 2003Applicant: Taiwn Semiconductor Manufacturing Co., Ltd.Inventors: Su-Yu Yeh, Chi-Bing Chen, Cheng-Yi Huang, Chao-Jie Tsai, Lu-Chang Chen, Hsing-Jui Lee
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Patent number: 6605812Abstract: A method for reducing a dinitrogen (N2) ion concentration in an ion implanter including providing an ion implanter having an ion source chamber for producing source ions said ion source chamber surrounded by a plurality of source magnets having a current supply for altering a position of said source ions; providing a gaseous source of material to the ion source chamber for ionization thereby creating a supply of source ions for implantation; creating a supply of source ions to include dinitrogen (N2) ions and nitrogen (N) ions supplied for implantation; and, increasing a current supply to at least one of the plurality of source magnets such that a ratio of dinitrogen (N2) ions to nitrogen (N) ions supplied for implantation is reduced.Type: GrantFiled: February 22, 2002Date of Patent: August 12, 2003Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Su-Yu Yeh, Chi-Bing Chen, Cheng-Yi Huang, Chao-Jie Tsai, Lu-Chang Chen, Hsing-Jui Lee