Patents by Inventor Hsing-Sen Wang

Hsing-Sen Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Balun built in multiple ceramic layers
    Patent number: 7005956
    Abstract: A balance-to-unbalance transformer (10), comprising an input terminal (11), a first output terminal (12), a second output terminal (13), a first circuit line comprising at least two capacitors (C1, C2) in parallel with each other and a first inductor L1 in series with the capacitors (C1, C2), wherein one electrode of each of the capacitors (C1, C2) are grounded, and a second circuit line comprising at least two capacitors (C3, C4) in series with each other and a second inductor (L2) in parallel with the capacitors (C3, C4), wherein one end of the second inductor (L2) is grounded. One end of the first circuit line and one end of the second circuit line are connected in parallel with the input terminal (11), and the other ends of the first and second circuit lines are the first and second output terminal, respectively.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: February 28, 2006
    Assignee: Delta Electronics, Inc.
    Inventor: Hsing-Sen Wang
  • Balun built in multiple ceramic layers
    Publication number: 20050083162
    Abstract: A balance-to-unbalance transformer (10), comprising an input terminal (11), a first output terminal (12), a second output terminal (13), a first circuit line comprising at least two capacitors (C1, C2) in parallel with each other and a first inductor L1 in series with the capacitors (C1, C2), wherein one electrode of each of the capacitors (C1, C2) are grounded, and a second circuit line comprising at least two capacitors (C3, C4) in series with each other and a second inductor (L2) in parallel with the capacitors (C3, C4), wherein one end of the second inductor (L2) is grounded. One end of the first circuit line and one end of the second circuit line are connected in parallel with the input terminal (11), and the other ends of the first and second circuit lines are the first and second output terminal, respectively.
    Type: Application
    Filed: December 23, 2003
    Publication date: April 21, 2005
    Inventor: Hsing-Sen Wang