Abstract: A dimmer circuit includes a light emitting module, a first current source, a digital-to-analog converter, a switch, a second current source and a pulse width modulation generator. The light emitting module is for emitting light according to a driving current. The first current source includes a first terminal coupled to a second terminal of the light emitting module. The digital-to-analog converter is for generating a DC voltage according to a DC dimming code signal to control the first current source. The switch includes a first terminal coupled to a second terminal of the light emitting module. The second current source includes a first terminal coupled to a second terminal of the switch. The PWM generator is for generating a PWM voltage according to the PWM dimming code signal to control the second current source.

Abstract: A conversion control circuit controls a power stage circuit of a switching power converter according to a first feedback signal and a second feedback signal, wherein the conversion control circuit includes an error amplifier circuit, a ramp signal generation circuit, a pulse width modulation circuit, and a quick response control circuit. The quick response control circuit performs a quick response control function, wherein the quick response control function includes: comparing the second feedback signal with at least one reference threshold to generate a quick response control signal; and when the second feedback signal crosses the reference threshold, adjusting a slope of a ramp signal according to the quick response control signal to accelerate an increase or decrease of the duty of a PWM signal, thereby accelerating the transient response of the switching power converter.

Abstract: A conversion control circuit, configured to control a switching power converter, includes a trigger signal generation circuit, an on-time control circuit, and a logic driver circuit. The trigger signal generation circuit is configured to generate a turn-on trigger signal. The on-time control circuit is configured to generate a turn-off trigger signal to determine the on-time and/or the off-time of a pulse width modulation (PWM) signal, and adjusts the on-time and/or the off-time according to the input voltage and the output voltage, such that the switching frequency of the switching power converter is adaptively adjusted according to a ratio between the output voltage and the input voltage. The logic driver circuit is configured to generate the PWM signal according to the turn-on trigger signal and the turn-off trigger signal, wherein the turn-on trigger signal enables the PWM signal, and the turn-off trigger signal disables the PWM signal.

Abstract: A spread spectrum switching converter converts an input power to an output power. The spread spectrum switching converter includes a pulse width modulation (PWM) circuit and a pulse omission control circuit. The PWM circuit generate an initial PWM signal according to a feedback signal related to the output power. The initial PWM signal controls at least one switch to switch an inductor to generate the output power. The pulse omission control circuit generates a pulse omission control signal to mask a portion of pulses of the initial PWM signal, to thereby generate an adjusted PWM signal. The pulse omission control circuit randomly adjusts the pulse width of the pulse omission control signal according to a random control signal, such that the adjusted PWM signal has a spread spectrum characteristic.

Abstract: A dimmer circuit includes a light emitting module, a first current source, a digital-to-analog converter, a switch, a second current source and a pulse width modulation generator. The light emitting module is for emitting light according to a driving current. The first current source includes a first terminal coupled to a second terminal of the light emitting module. The digital-to-analog converter is for generating a DC voltage according to a DC dimming code signal to control the first current source. The switch includes a first terminal coupled to a second terminal of the light emitting module. The second current source includes a first terminal coupled to a second terminal of the switch. The PWM generator is for generating a PWM voltage according to the PWM dimming code signal to control the second current source.

Abstract: A light emitting device array circuit capable of reducing ghost image includes: a light emitting device array, plural scan line switch circuits, and a driver circuit. The light emitting device array includes plural light emitting devices arranged in plural scan lines and plural data lines. In one frame, plural scan line switch circuits respectively electrically connect plural scan nodes in plural corresponding scan lines to a scan conduction voltage in a non-overlapping sequential order. Data line buffer circuits of the driver circuit provide predetermined dimming levels to corresponding data nodes respectively according to data operation signals. A pre-discharge control amplifier circuit of the driver circuit is coupled to the plural scan nodes and provides a pre-discharge level to at least one predetermined scan node during a predetermined pre-discharge time period according to a pre-discharge signal.

Abstract: A light emitting device array circuit capable of reducing ghost image includes: a light emitting device array, plural scan line switch circuits, and a driver circuit. The light emitting device array includes plural light emitting devices arranged in plural scan lines and plural data lines. In one frame, plural scan line switch circuits respectively electrically connect plural scan nodes in plural corresponding scan lines to a scan conduction voltage in a non-overlapping sequential order. Data line buffer circuits of the driver circuit provide predetermined dimming levels to corresponding data nodes respectively according to data operation signals. A pre-discharge control amplifier circuit of the driver circuit is coupled to the plural scan nodes and provides a pre-discharge level to at least one predetermined scan node during a predetermined pre-discharge time period according to a pre-discharge signal.

Abstract: A power conversion apparatus includes: a power supply circuit, a load switch and a control circuit. The power supply circuit generates a first power. The load switch controls the power path from the power supply circuit to a load. The control circuit generates a switching control signal to control a conduction level of the load switch according to an enable signal. The control circuit controls a level of the switching control signal to soft start from a first level to a second level. During the soft start period, the switching control signal has plural waveform segments including a first waveform segment and a second waveform segment. A level variation speed of the first waveform segment is higher than a level variation speed of the second waveform segment. The first waveform segment level precedes the second waveform segment level.

Abstract: A power conversion apparatus includes: a power supply circuit, a load switch and a control circuit. The power supply circuit generates a first power. The load switch controls the power path from the power supply circuit to a load. The control circuit generates a switching control signal to control a conduction level of the load switch according to an enable signal. The control circuit controls a level of the switching control signal to soft start from a first level to a second level. During the soft start period, the switching control signal has plural waveform segments including a first waveform segment and a second waveform segment. A level variation speed of the first waveform segment is higher than a level variation speed of the second waveform segment. The first waveform segment level precedes the second waveform segment level.

Abstract: A display apparatus includes a timing controller and a gate-driver on array (GOA) control circuit. The timing controller generates a frame synchronization signal. The GOA control circuit is coupled to the timing controller and includes a scan signal management circuit and a level shifter. The scan signal management circuit generates a scan signal management signal according to the frame synchronization signal, a predetermined panel parameter, and an operation clock signal. The scan signal management circuit includes a storage unit which stores the predetermined panel parameter. The level shifter generates a scan control signal according to the scan signal management signal to control a GOA of a display panel circuit. The GOA generates a gate driving signal to control a vertical scan operation of the display panel circuit.

Abstract: A driver circuit supplies a positive voltage and a negative voltage to a load. The driver circuit includes: a positive power conversion circuit, coupled to the load, and generating the positive voltage according to an input voltage; a negative power conversion circuit, coupled to the positive power conversion circuit and the load, and generating the negative voltage according to the positive voltage; and a headroom adaptive adjustment circuit, coupled to the positive power conversion circuit and the load, and generating an adjustment signal according to one or more of a load current flowing through the load, the positive voltage Vp and the negative voltage Vn. The adjustment signal is sent to the positive power conversion circuit to adjust a regulation target of the positive voltage.

Abstract: The present invention provides a display apparatus, including: a display panel circuit which includes a panel load line and performs a scanning display operation; and a panel driving circuit. The panel driving circuit determines at least a test phase and a scanning display phase according to a display control signal generated by a timing control circuit, wherein the test phase is a partial time period when the panel driving circuit does not perform the scanning display operation. The panel driving circuit generates a test driving signal on the panel load line, and detects an electronic characteristic of the display panel circuit so as to determine a failure item thereof during the test phase according to a pre-determined test instruction. The panel driving circuit generates a display driving signal on the panel load line for the scanning display operation according to the display control signal during the scanning display phase.

Abstract: A display apparatus includes a timing controller and a gate-driver on array (GOA) control circuit. The timing controller generates a frame synchronization signal. The GOA control circuit is coupled to the timing controller and includes a scan signal management circuit and a level shifter. The scan signal management circuit generates a scan signal management signal according to the frame synchronization signal, a predetermined panel parameter, and an operation clock signal. The scan signal management circuit includes a storage unit which stores the predetermined panel parameter. The level shifter generates a scan control signal according to the scan signal management signal to control a GOA of a display panel circuit. The GOA generates a gate driving signal to control a vertical scan operation of the display panel circuit.

Abstract: A Gamma curve correction method for an LCD sets a ground potential of the LCD as a common voltage and adjusts at least one of a plurality of positive Gamma voltages and a plurality of negative Gamma voltages of the LCD such that the central voltage value of a Gamma curve established by the positive Gamma voltages and the negative Gamma voltages becomes closer to the common voltage. As a result, flickers existing in the images of the LCD are improved.

Abstract: The present invention provides a display apparatus, including: a display panel circuit which includes a panel load line and performs a scanning display operation; and a panel driving circuit. The panel driving circuit determines at least a test phase and a scanning display phase according to a display control signal generated by a timing control circuit, wherein the test phase is a partial time period when the panel driving circuit does not perform the scanning display operation. The panel driving circuit generates a test driving signal on the panel load line, and detects an electronic characteristic of the display panel circuit so as to determine a failure item thereof during the test phase according to a pre-determined test instruction. The panel driving circuit generates a display driving signal on the panel load line for the scanning display operation according to the display control signal during the scanning display phase.

Abstract: The present invention provides a display apparatus, including: a display panel circuit which includes a panel load line and performs a scanning display operation; and a panel driving circuit. The panel driving circuit determines at least a test phase and a scanning display phase according to a display control signal generated by a timing control circuit, wherein the test phase is a partial time period when the panel driving circuit does not perform the scanning display operation. The panel driving circuit generates a test driving signal on the panel load line, and detects an electronic characteristic of the display panel circuit so as to determine a failure item thereof during the test phase according to a pre-determined test instruction. The panel driving circuit generates a display driving signal on the panel load line for the scanning display operation according to the display control signal during the scanning display phase.

Abstract: The present invention provides a display apparatus, including: a display panel circuit which includes a panel load line and performs a scanning display operation; and a panel driving circuit. The panel driving circuit determines at least a test phase and a scanning display phase according to a display control signal generated by a timing control circuit, wherein the test phase is a partial time period when the panel driving circuit does not perform the scanning display operation. The panel driving circuit generates a test driving signal on the panel load line, and detects an electronic characteristic of the display panel circuit so as to determine a failure item thereof during the test phase according to a pre-determined test instruction. The panel driving circuit generates a display driving signal on the panel load line for the scanning display operation according to the display control signal during the scanning display phase.