Abstract: In each row of a nonvolatile memory array, the select gates of all the memory cells are connected together and are used to select a row for memory access. The control gates of each row are also connected together, and the source regions of each row are connected together. Also, the control gates of plural rows are connected together, and the source regions of plural rows are connected together, but if the source regions of two rows are connected together, then their control gates are not connected together. If one of the two rows is being accessed but the other one of the two rows is not being accessed, their control gates are driven to different voltages, reducing the probability of a punch-through in the non-accessed row.

Abstract: In each row of a nonvolatile memory array, the select gates of all the memory cells are connected together and are used to select a row for memory access. The control gates of each row are also connected together, and the source regions of each row are connected together. Also, the control gates of plural rows are connected together, and the source regions of plural rows are connected together, but if the source regions of two rows are connected together, then their control gates are not connected together. If one of the two rows is being accessed but the other one of the two rows is not being accessed, their control gates are driven to different voltages, reducing the probability of a punch-through in the non-accessed row.

Abstract: In a nonvolatile memory, a floating gate includes a portion of a conductive layer (150), and also includes conductive spacers (610). The spacers increase the capacitive coupling between the floating gate and the control gate (170).

Abstract: In a nonvolatile memory, a floating gate includes a portion of a conductive layer (150), and also includes conductive spacers (610). The spacers increase the capacitive coupling between the floating gate and the control gate (170).

Abstract: In each row of a nonvolatile memory array, the select gates of all the memory cells are connected together and are used to select a row for memory access. The control gates of each row are also connected together, and the source regions of each row are connected together. Also, the control gates of plural rows are connected together, and the source regions of plural rows are connected together, but if the source regions of two rows are connected together, then their control gates are not connected together. If one of the two rows is being accessed but the other one of the two rows is not being accessed, their control gates are driven to different voltages, reducing the probability of a punch-through in the non-accessed row.

Abstract: In each row of a nonvolatile memory array, the select gates of all the memory cells are connected together and are used to select a row for memory access. The control gates of each row are also connected together, and the source regions of each row are connected together. Also, the control gates of plural rows are connected together, and the source regions of plural rows are connected together, but if the source regions of two rows are connected together, then their control gates are not connected together. If one of the two rows is being accessed but the other one of the two rows is not being accessed, their control gates are driven to different voltages, reducing the probability of a punch-through in the non-accessed row.

Abstract: In a nonvolatile memory, a floating gate includes a portion of a conductive layer (150), and also includes conductive spacers (610). The spacers increase the capacitive coupling between the floating gate and the control gate (170).

Abstract: In a nonvolatile memory, a floating gate includes a portion of a conductive layer (150), and also includes conductive spacers (610). The spacers increase the capacitive coupling between the floating gate and the control gate (170).

Abstract: A logical latch is permanently programmable to a selected state for use as a control circuit with extremely low power consumption in an integrated circuit.

Abstract: An integrated circuit memory device is provided which includes a memory array including multiple memory cores, each core including a two-dimensional (x,y) array of memory cells, the memory array further including a plurality of x-lines and a plurality of y-lines; an address bus including a first bus oriented with a y-dimension and a second bus oriented with an x-dimension; and x-address generator; a y-address generator; a multiplexer circuit for operatively coupling one of the x-address generator and the y-address generator to the address bus; a plurality of y-address decoders each for producing decoded y-information to at least one of the plurality of y-lines; a plurality of separate x-address decoders each for producing decoded x-information for at least one of the plurality of x-lines; and a plurality of separate sustain circuits each for sustaining decoded x-information produced by at least one x-decoder.

Abstract: An improved read-only/read-write semiconductor memory of the type that includes a semiconductor substrate with dopant atoms of a first conductivity type, a pair of spaced-apart charge storage regions at the surface of the substrate, a bit line at the surface of the substrate spaced apart from the charge storage region, respective MOSFET transistor gate regions at the surface of the substrate between the bit line and the charge storage regions, and a conductor over the storage regions; the improvement comprising dopant atoms of a second conductivity type in one of the storage regions, and dopant atoms of the first conductivity type in the other of the storage regions having a greater doping concentration than is in the body of the substrate; and circuitry for applying a read-write mode voltage to the conductor to permit charge to be stored in both of the storage regions, and for applying a read-only mode voltage to the conductor to permit charge to be stored in the one storage region and simultaneously prevent

Abstract: Disclosed is a circuit for restoring charge to the cells of a semiconductor memory during a read operation. A respective one of the circuits couples to each of the bit lines of the memory. No power is dissipated in those circuits which couple the bit lines that are to be discharged during a read. Also, the circuit includes only three transistors, and thus occupies a minimal amount of chip space. In addition, the circuit is operable in response to only a single clocking signal. Further, the circuit is operable over a relatively large range of precharge voltage levels for the bit lines such as 3 volts to 7 volts.

Abstract: Disclosed is a RAM that includes a semiconductor substrate having P-type dopant impurity atoms and having a major surface. A plurality of spaced apart regions of N-type atoms lie within a predetermined area on the surface to define storage regions for the cells of the memory. An insulating layer of substantially uniform thickness with a conductive layer lying thereon completely covers the predetermined area except for a plurality of elongated openings which extend outward from each of the storage regions. A layer of P-type dopant atoms lie at substantially the same level as the storage regions throughout that portion of the substrate that is beneath the insulating layer. By this structure, the perimeter of a transfer gate that exhibits essentially no narrow channel width effect is defined from each storage region by the respective openings.