Abstract: A semiconductor fabrication process for forming a gate dielectric includes depositing a high-k dielectric stack including incorporating nitrogen into the high-k dielectric stack in-situ. A top high-k dielectric is formed overlying the dielectric stack and the dielectric stack and the top dielectric are annealed. Depositing the dielectric stack may include depositing a plurality of high-k dielectric layers where each layer is formed in a distinct processing step or set of steps. Depositing one of the dielectric layers may include performing a plurality of atomic layer deposition processes to form a plurality of high-k sublayers, wherein each sublayer is a monolayer film. Depositing the plurality of sublayers may include depositing a nitrogen free sublayer and depositing a nitrogen bearing sublayer. Depositing the nitrogen free sublayer may include pulsing an ALD chamber with HfCl4, purging the chamber with an inert, pulsing the chamber with an H2O or D2O, and purging the chamber with an inert.

Abstract: A metal oxide is formed over a high quality oxide which has been deposited over a substrate. An anneal drives a reaction to form a metal oxysilicon nitride layer which is then used as a part of a gate stack. The novel integration scheme allows for improved scalablity of devices as well as improved leakage currents.

Abstract: A gate dielectric structure (201) fabrication process includes forming a transitional dielectric film (205) overlying a silicon oxide film (204). A high dielectric constant film (206) is then formed overlying an upper surface of the transitional dielectric film (205). The composition of the transitional dielectric film (205) at the silicon oxide film (204) interface primarily comprises silicon and oxygen. The high K dielectric (206) and the composition of the transitional dielectric film (205) near the upper surface primarily comprise a metal element and oxygen. Forming the transitional dielectric film (205) may include forming a plurality of transitional dielectric layers (207) where the composition of each successive transitional dielectric layer (207) has a higher concentration of the metal element and a lower concentration of silicon.

Abstract: A method of forming an electronic device includes etching a portion of a first gate dielectric layer to reduce a thickness of the gate dielectric layer within that portion. In one embodiment, portions not being etched may be covered by mask. In another embodiment, different portions may be etched during different times to give different thicknesses for the first gate dielectric layer. In a particular embodiment, a second gate dielectric layer may be formed over the first gate dielectric layer after etching the portion. The second gate dielectric layer can have a dielectric constant greater than the dielectric constant of the first gate dielectric layer. Subsequent gate electrode and source/drain region formation can be performed to form a transistor structure.

Abstract: A gate dielectric is treated with a nitridation step and an anneal. After this, an additional nitridation step and anneal is performed. The second nitridation and anneal results in an improvement in the relationship between gate leakage current density and current drive of the transistors that are ultimately formed.

Abstract: A semiconductor fabrication annealing process includes depositing a high dielectric constant gate dielectric over a substrate and annealing the gate dielectric. Annealing the gate dielectric includes exposing the gate dielectric to an inert ambient and ramping the inert ambient to an annealing temperature. A passivating gas is then introduced into the ambient while maintaining the ambient at the annealing temperature. This passivating ambient is then maintained at the annealing temperature for a specified duration. While maintaining the presence of the passivating gas in the ambient, the ambient temperature is then ramped down from the annealing temperature to a second temperature, which is preferably less than 100° C. The passivating gas is preferably hydrogen gas, deuterium gas, or a combination of the two. The annealing temperature is preferably greater than approximately 470° C.

Abstract: A semiconductor fabrication includes forming a gate dielectric overlying a semiconductor substrate and depositing a metal gate film overlying the gate dielectric. Following deposition of the metal gate film, nitrogen, carbon, and/or oxygen is introduced into the metal gate film by exposing the metal gate film to a nitrogen, carbon, and/or oxygen bearing plasma. Thereafter, the nitrogenated/oxygenated/carbonated metal gate film is patterned to form a transistor gate electrode. Depositing the metal gate film is preferably done with a low energy process such as atomic layer deposition (ALD) or metal organic chemical vapor deposition (MOCVD) to reduce damage to the underlying gate dielectric. The metal gate film for NMOS devices is preferably a compound of nitrogen and Ti, W, or Ta. A second metal gate film may be used for PMOS devices. This second metal gate film is preferably a compound of oxygen and Ir, Ru, Mo, or Re.

Abstract: A method for forming a dielectric is disclosed. The method comprises forming a first dielectric layer over semiconductor material. A diffusion barrier material is introduced into the first dielectric layer. Lastly, a second dielectric layer is formed over the first dielectric layer after the introducing.

Abstract: A semiconductor device has a P channel gate stack comprising a first metal type and a second metal type over the first metal type and an N channel gate stack comprising the second metal type in direct contact with a gate dielectric/etch stop layer stack. The N channel gate stack and the P channel gate stack are etched by a dry etch. Either the gate dielectric or etch stop can be in contact with the substrate. The etch stop layer prevents the dry etch of the first and second metal layers from etching through the gate dielectric and gouging the underlying substrate.