Patents by Inventor Hsing-Yi Chien

Hsing-Yi Chien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Suppression of hot-carrier effects using double well for thin gate oxide LDMOS embedded in HV process
    Patent number: 8004038
    Abstract: A semiconductor device includes a first high-voltage well having a first dopant disposed in a semiconductor substrate; a second high-voltage well having a second dopant disposed in the semiconductor substrate, laterally adjacent to the first high-voltage well; a low-voltage well having the second dopant disposed overlying the second high-voltage well; a drain region having the first dopant disposed in the first high-voltage well; a source having the first dopant disposed in the low-voltage well; and a gate disposed on the semiconductor substrate and laterally between the source and the drain, wherein the gate includes a thin gate dielectric and a gate electrode.
    Type: Grant
    Filed: May 22, 2006
    Date of Patent: August 23, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsing-Yi Chien, Yu-Chang Jong, Te-Yin Hsia, Ruey-Shin Liu
  • SUPPRESSION OF HOT-CARRIER EFFECTS USING DOUBLE WELL FOR THIN GATE OXIDE LDMOS EMBEDDED IN HV PROCESS
    Publication number: 20070267693
    Abstract: A semiconductor device includes a first high-voltage well having a first dopant disposed in a semiconductor substrate; a second high-voltage well having a second dopant disposed in the semiconductor substrate, laterally adjacent to the first high-voltage well; a low-voltage well having the second dopant disposed overlying the second high-voltage well; a drain region having the first dopant disposed in the first high-voltage well; a source having the first dopant disposed in the low-voltage well; and a gate disposed on the semiconductor substrate and laterally between the source and the drain, wherein the gate includes a thin gate dielectric and a gate electrode.
    Type: Application
    Filed: May 22, 2006
    Publication date: November 22, 2007
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsing-Yi Chien, Yu-Chang Jong, Ruey-Hsin Liu, Te-Yin Hsia