Abstract: An electronic device package includes a carrying board, an electronic device, a first insulating layer, and a barrier layer. The carrying board includes a central area, an inner edge area, and an outer edge area. The inner edge area is located between the central area and the outer edge area. The electronic device is located in the central area. The first insulating layer is located on the carrying board and overlapped with the electronic device and extends from the central area to the inner edge area. The barrier layer is located on the carrying board. Here, the barrier layer includes a sidewall contact portion and an extending portion. The sidewall contact portion surrounds a side surface of the first insulating layer, and the extending portion extends from the sidewall contact portion to the outer edge area in a direction away from the first insulating layer.

Abstract: A pixel structure includes data lines disposed along a first direction, scan lines disposed along a second direction and pixel units periodically disposed along the first and the second directions. In a first pixel unit, a first switch element is coupled to a first scan line and a first data line, the second switch element is coupled to the first scan line, and a third switch element is coupled to the first scan line. In a second pixel unit, a fourth switch element is coupled to a second scan line, the first data line and the second switch element, and a fifth switch element is electrically coupled to the second scan line and the third switch element. In a third pixel unit, a sixth switch element is coupled to a third scan line, the first data line and the fifth switch element.

Abstract: A pixel structure includes data lines disposed along a first direction, scan lines disposed along a second direction and pixel units periodically disposed along the first and the second directions. In a first pixel unit, a first switch element is coupled to a first scan line and a first data line, the second switch element is coupled to the first scan line, and a third switch element is coupled to the first scan line. In a second pixel unit, a fourth switch element is coupled to a second scan line, the first data line and the second switch element, and a fifth switch element is electrically coupled to the second scan line and the third switch element. In a third pixel unit, a sixth switch element is coupled to a third scan line, the first data line and the fifth switch element.

Abstract: An electronic device package includes a carrying board, an electronic device, a first insulating layer, and a barrier layer. The carrying board includes a central area, an inner edge area, and an outer edge area. The inner edge area is located between the central area and the outer edge area. The electronic device is located in the central area. The first insulating layer is located on the carrying board and overlapped with the electronic device and extends from the central area to the inner edge area. The barrier layer is located on the carrying board. Here, the barrier layer includes a sidewall contact portion and an extending portion. The sidewall contact portion surrounds a side surface of the first insulating layer, and the extending portion extends from the sidewall contact portion to the outer edge area in a direction away from the first insulating layer.

Abstract: An organic-inorganic hybrid transistor comprises a flexible substrate, a gate electrode, an organic gate dielectric layer, an oxide semiconductor layer, a first passivation layer, a source electrode and a drain electrode. The gate electrode is disposed on the flexible substrate. The organic gate dielectric layer covers the gate electrode and a portion of the flexible substrate. The oxide semiconductor layer is disposed over the organic gate dielectric layer. The first passivation layer is interposed between and in contact with the oxide semiconductor layer and the organic gate dielectric layer. The source electrode and the drain electrode are respectively connected to different sides of the oxide semiconductor layer.

Abstract: An active device includes a gate, a gate insulation layer, a channel layer, a first passivation layer, a second passivation layer, a source and a drain. The gate insulation layer is disposed on the substrate and covers the gate. The channel layer is disposed on the gate insulation layer and has a semiconductor section disposed corresponding to the gate and a conductive section located around the semiconductor section. The first passivation layer is disposed on the channel layer and covers the semiconductor section. The second passivation layer is disposed on and covers the first passivation layer. The source and the drain are disposed on the gate insulation layer, and extended along peripheries of the conductive section, the first and the second passivation layers to be disposed on the second passivation layer. A portion of the second passivation layer is exposed between the source and the drain.

Abstract: An organic semiconductor device includes a carrier, a source, a drain, an organic semiconductor single-crystalline channel layer, an organic insulation layer and a gate. The source and the drain are disposed on an upper surface of the carrier. The source and the drain are disposed in parallel and a portion of the carrier is exposed between the source and the drain. The organic semiconductor single-crystalline channel layer is disposed on the upper surface of the carrier and covers a portion of the source, a portion of the drain and the portion of the carrier exposed by the source and the drain. The organic insulation layer covers the carrier, the source, the drain and the organic semiconductor single-crystalline channel layer. The gate is disposed on the organic insulation layer and corresponds to a position of the portion of the carrier exposed by the source and the drain.

Abstract: An organic light-emitting display device includes an active array substrate, an encapsulating layer, an organic light-emitting layer, an absorption layer and a sealant. The encapsulating layer is opposite to the active array substrate, and the encapsulating layer has an inner surface facing the active array substrate. The organic light-emitting layer is disposed on the active array substrate. The absorption layer is configured to absorb at least one of moisture and oxygen, and is positioned on the inner surface of the encapsulating layer.

Abstract: A compensation method for a light emitting diode (LED) circuit including a first transistor, a second transistor, a capacitor, and a LED is illustrated. A first end as a control end of the first transistor is connected to one end of the second transistor and the capacitor, and a second end of the first transistor is connected to the LED. A width to length (W/L) ratio of the second transistor is less than one. An initial control voltage is applied to a control end of the second transistor, and the current output voltage of the LED is correspondingly measured. If a difference between the current output voltage and an initial output voltage exceeds a predetermined value, a compensation voltage, which is a summation of the initial control voltage and the difference, is applied to the control end of the second transistor.

Abstract: A transistor and a manufacturing method thereof are provided. The transistor includes a first gate, a second gate disposed on one side of the first gate, a first semiconductor layer, a second semiconductor layer, an oxide layer, a first insulation layer, a second insulation layer, a source, and a drain. The first semiconductor layer is disposed between the first and second gates; the second semiconductor layer is disposed between the first semiconductor layer and the second gate. The oxide layer is disposed between the first semiconductor layer and the second semiconductor layer. The first insulation layer is disposed between the first gate and the first semiconductor layer; the second insulation layer is disposed between the second gate and the second semiconductor layer. The source and the drain are disposed between the first insulation layer and the second insulation layer and respectively disposed on opposite sides of the oxide layer.

Abstract: An organic semiconductor device includes a carrier, a source, a drain, an organic semiconductor single-crystalline channel layer, an organic insulation layer and a gate. The source and the drain are disposed on an upper surface of the carrier. The source and the drain are disposed in parallel and a portion of the carrier is exposed between the source and the drain. The organic semiconductor single-crystalline channel layer is disposed on the upper surface of the carrier and covers a portion of the source, a portion of the drain and the portion of the carrier exposed by the source and the drain. The organic insulation layer covers the carrier, the source, the drain and the organic semiconductor single-crystalline channel layer. The gate is disposed on the organic insulation layer and corresponds to a position of the portion of the carrier exposed by the source and the drain.

Abstract: A transistor and a manufacturing method thereof are provided. The transistor includes a first gate, a second gate disposed on one side of the first gate, a first semiconductor layer, a second semiconductor layer, an oxide layer, a first insulation layer, a second insulation layer, a source, and a drain. The first semiconductor layer is disposed between the first and second gates; the second semiconductor layer is disposed between the first semiconductor layer and the second gate. The oxide layer is disposed between the first semiconductor layer and the second semiconductor layer. The first insulation layer is disposed between the first gate and the first semiconductor layer; the second insulation layer is disposed between the second gate and the second semiconductor layer. The source and the drain are disposed between the first insulation layer and the second insulation layer and respectively disposed on opposite sides of the oxide layer.

Abstract: A thin film transistor (TFT) array substrate includes a substrate, a gate electrode layer disposed on the substrate, an insulating layer, an oxide semiconductor layer disposed on the insulating layer, a source/drain electrode layer, an organic-acrylic photoresist layer, a passivation layer and an electrically conductive layer. The insulating layer is disposed on the gate electrode layer and the substrate. The source/drain electrode layer is disposed on the insulating layer and the oxide semiconductor layer, and a gap is formed through the source/drain electrode layer for exposing the oxide semiconductor layer therethrough. The organic-acrylic photoresist layer covers the source/drain electrode layer. The passivation layer is disposed on the substrate, the oxide semiconductor layer and the organic-acrylic photoresist layer.

Abstract: A compensation method for a light emitting diode (LED) circuit including a first transistor, a second transistor, a capacitor, and a LED is illustrated. A first end as a control end of the first transistor is connected to one end of the second transistor and the capacitor, and a second end of the first transistor is connected to the LED. A width to length (W/L) ratio of the second transistor is less than one. An initial control voltage is applied to a control end of the second transistor, and the current output voltage of the LED is correspondingly measured. If a difference between the current output voltage and an initial output voltage exceeds a predetermined value, a compensation voltage, which is a summation of the initial control voltage and the difference, is applied to the control end of the second transistor.

Abstract: A dynamic bandwidth allocation method of an Ethernet passive optical network, comprises a predictor and a rule of QoS-promoted dynamic bandwidth allocation (PQ-DBA); the predictor predicts a client behavior and numbers of various kinds of packets by using a pipeline scheduling predictor consisted of a pipelined recurrent neural network (PRNN), and a learning rule of the extended recursive least squares (ERLS); the present invention establishes a better QoS traffic management for the OLT-allocated ONU bandwidth and client packets sent by priority.

Abstract: A dynamic bandwidth allocation method of an Ethernet passive optical network, comprises a predictor and a rule of QoS-promoted dynamic bandwidth allocation (PQ-DBA); the predictor predicts a client behavior and numbers of various kinds of packets by using a pipeline scheduling predictor consisted of a pipelined recurrent neural network (PRNN), and a learning rule of the extended recursive least squares (ERLS); the present invention establishes a better QoS traffic management for the OLT-allocated ONU bandwidth and client packets sent by priority.