Abstract: A memory cell includes a current-steering device, a phase-change material disposed thereover, and a heating element and/or a cooling element.

Abstract: A semiconductor transistor is formed as follows. A gate electrode is formed over but is insulated from a semiconductor body region. A first layer of insulating material is formed over the gate electrode and the semiconductor body region. A second layer of insulating material different from the first layer of insulating material is formed over the first layer of insulating material. Only the second layer of insulating material is etched to form spacers along the side-walls of the gate electrode. Impurities are implanted through the first layer of insulating material to form a source region and a drain region in the body region. A substantial portion of those portions of the first layer of insulting material extending over the source and drain regions is removed.

Abstract: A semiconductor transistor which is not capable of storing data is formed as follows. An insulating layer is formed over a silicon region. An undoped polysilicon layer is formed over and in contact with the insulating layer. A doped polysilicon layer is formed over and in contact with the undoped polysilicon layer such that at least two edges of the doped polysilicon layer vertically line up with corresponding edges of the undoped polysilicon layer to thereby form sidewalls, and the doped and undoped polysilicon layers form a gate of the transistor. After the doped polysilicon layer is formed, source and drain regions are formed in the silicon region. Dopants from the doped polysilicon layer migrate into the undoped polysilicon layer thereby doping the undoped polysilicon layer.

Abstract: A gate electrode is formed over but insulated from a semiconductor body region for each of first and second transistors. A DDD implant is carried out to from DDD source and DDD drain regions in the body region for the first transistor. After the DDD implant, off-set spacers are formed along side-walls of the gate electrode of each of the first and second transistors. After forming the off-set spacers, a LDD implant is carried out to from LDD source and drain regions in the body region for the second transistor. After the LDD implant, main spacers are formed adjacent the off-set spacers of at least the second transistor. After forming the main spacers, a source/drain implant is carried out to form a highly doped region within each of the DDD drain and source regions and the LDD drain and source regions.

Abstract: A method of erasing a non-volatile memory includes applying a first potential of first polarity to a control gate; applying a second potential of second polarity to a bulk region, the second potential being an N magnitude; and applying a third potential of second polarity to a source region, the third potential being an M magnitude, wherein the N and M are substantially the same.

Abstract: A method of erasing a non-volatile memory includes applying a first potential of first polarity to a control gate; applying a second potential of second polarity to a bulk region, the second potential being an N magnitude; and applying a third potential of second polarity to a source region, the third potential being an M magnitude, wherein the N and M are substantially the same.

Abstract: A memory device, such as a flash EEPROM, employs a high energy implantation to form common source line, avoiding the necessity of self-aligned source etch processes. The use of the high energy implantation, and avoiding the etching process, provides for greater cell uniformity, and better V.sub.T distribution.

Abstract: A method of forming and removing spacers used to mask lightly doped drain (LDD) regions in the formation of a field effect transistor (FET) involves depositing a thin oxide layer over the active region of a substrate and a gate structure formed on the active region. A polysilicon film is provided over the oxide and then doped using a POCl.sub.3 dopant. The polysilicon layer is then etched to form spacers at the ends of the gate and the spacers are used to mask lightly doped drain regions in the substrate during the implantation of source and drain regions. After the implant to form the source and drain regions, the device is subjected to a rapid thermal annealing for approximately 20-60 seconds at approximately 900.degree. C. in an inert atmosphere to cure any damage to the oxide layer which occurs during the source/drain implant. Curing the oxide layer reduces the etch rate of the oxide layer for an etchant which is designed to selectively etch the polysilicon spacers faster than it etches the oxide layer.

Abstract: A process of forming a floating gate field-effect transistor having a multi-layer control gate line is disclosed. The multi-layer control gate line includes a first polysilicon layer, a silicide layer provided on the first polysilicon layer, and a second polysilicon layer provided on the silicide layer. The first and second polysilicon layers are formed as undoped polysilicon to improve the adhesion of the polysilicon layers to the silicide layers sandwiched therebetween. After all three layers are formed, the polysilicon layers are doped in an environment including POCl.sub.3. Because the first and second polysilicon layers are formed as undoped layers, all three layers of the control gate line may be formed using a single pump-down.

Abstract: A method for constructing titanium silicide integrated circuit gate electrodes and interconnections is disclosed. The method finds particularly useful applications in metal-oxide semiconductor integrated circuit fabrication. Following standard active and passive circuit component construction, a thin film of titanium is overlayed on the die structure covering thereby the pre-patterned polysilicon gates and interconnections. The die is then rapidly heated and baked to form a silicide layer superposing said polysilicon. The undesired titanium layer over other areas can be stripped using simple ammonium hydroxide/hydrogen etching and cleaning solution. Titanium silicide electrodes and interconnections are self-aligned and have a sheet resistance of 1 to 5 ohms per square.