Patents by Inventor HSIN-WEI WANG
HSIN-WEI WANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128232Abstract: A semiconductor package includes a first semiconductor die, an encapsulant, a high-modulus dielectric layer and a redistribution structure. The first semiconductor die includes a conductive post in a protective layer. The encapsulant encapsulates the first semiconductor die, wherein the encapsulant is made of a first material. The high-modulus dielectric layer extends on the encapsulant and the protective layer, wherein the high-modulus dielectric layer is made of a second material. The redistribution structure extends on the high-modulus dielectric layer, wherein the redistribution structure includes a redistribution dielectric layer, and the redistribution dielectric layer is made of a third material. The protective layer is made of a fourth material, and a ratio of a Young's modulus of the second material to a Young's modulus of the fourth material is at least 1.5.Type: ApplicationFiled: December 28, 2023Publication date: April 18, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Ding Wang, Yen-Fu Su, Hao-Cheng Hou, Jung-Wei Cheng, Chien-Hsun Lee, Hsin-Yu Pan
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Publication number: 20240123311Abstract: An artificial shuttlecock includes a ball head, a plurality of feathers, and a plurality of stems. Each of the feathers includes a notch. The notch is disposed on an outer edge of the feather. A ball head end of the stem is connected to the ball head, and a feather end is connected to the feather. The stem includes a body, which tapers from the end close to the ball end to the feather end. The end of the body close to the ball end has a first width, and the body has a second width at the feather. The first width is between 2.1 mm and 2.4 mm, and the second width is between 0.4 mm and 0.6 mm.Type: ApplicationFiled: October 6, 2023Publication date: April 18, 2024Inventors: SHU-JUNG CHEN, TZU-WEI WANG, HSIN-CHEN WANG
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Publication number: 20240130257Abstract: Devices and method for forming a switch including a heater layer including a first heater pad, a second heater pad, and a heater line connecting the first heater pad and the second heater pad, a phase change material (PCM) layer positioned in a same vertical plane as the heater line, and a floating spreader layer including a first portion positioned in the same vertical plane as the heater line and the PCM layer, in which the first portion has a first width that is less than or equal to a distance between proximate sidewalls of the first heater pad and the second heater pad.Type: ApplicationFiled: April 21, 2023Publication date: April 18, 2024Inventors: Fu-Hai LI, Yi Ching ONG, Hsin Heng WANG, Tsung-Hao YEH, Yu-Wei TING, Kuo-Pin CHANG, Hung-Ju LI, Kuo-Ching HUANG
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Patent number: 11961769Abstract: A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions.Type: GrantFiled: November 7, 2022Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Kuo-Hsiu Hsu, Yu-Kuan Lin, Feng-Ming Chang, Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang
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Patent number: 11956948Abstract: A memory device includes a substrate, a first transistor and a second transistor, a first word line, a second word line, and a bit line. The first transistor and the second transistor are over the substrate and are electrically connected to each other, in which each of the first and second transistors includes first semiconductor layers and second semiconductor layers, a gate structure, and source/drain structures, in which the first semiconductor layers are in contact with the second semiconductor layers, and a width of the first semiconductor layers is narrower than a width of the second semiconductor layers. The first word line is electrically connected to the gate structure of the first transistor. The second word line is electrically connected to the gate structure of the second transistor. The bit line is electrically connected to a first one of the source/drain structures of the first transistor.Type: GrantFiled: April 1, 2022Date of Patent: April 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Wen Su, Yu-Kuan Lin, Shih-Hao Lin, Lien-Jung Hung, Ping-Wei Wang
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Publication number: 20240006327Abstract: IC die package routing structures including a bulk layer of a first metal composition on an underlying layer of a second metal composition. The lower layer may be sputter deposited to a thickness sufficient to support plating of the bulk layer upon a first portion of the lower layer. Following the plating process, a second portion of the lower layer may be removed selectively to the bulk layer. Multiple IC die may be attached to the package with the package routing structures responsible for the transmission of high-speed data signals between the multiple IC die. The package may be further assembled to a host component that conveys power to the IC die package.Type: ApplicationFiled: July 1, 2022Publication date: January 4, 2024Applicant: Intel CorporationInventors: Jeremy Ecton, Aleksandar Aleksov, Kristof Darmawikarta, Robert A. May, Brandon Marin, Benjamin Duong, Suddhasattwa Nad, Hsin-Wei Wang, Leonel Arana, Darko Grujicic
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Patent number: 11817349Abstract: A conductive route for an integrated circuit assembly may be formed using a sequence of etching and passivation steps through layers of conductive material, wherein the resulting structure may include a first route portion having a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, an etch stop structure on the first route portion, a second route portion on the etch stop layer, wherein the second route portion has a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, and a passivating layer abutting the at least one side surface of the second route portion.Type: GrantFiled: March 5, 2020Date of Patent: November 14, 2023Assignee: Intel CorporationInventors: Jeremy Ecton, Brandon C. Marin, Leonel Arana, Matthew Tingey, Oscar Ojeda, Hsin-Wei Wang, Suddhasattwa Nad, Srinivas Pietambaram, Gang Duan
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Patent number: 11528811Abstract: Techniques and mechanisms for providing anisotropic etching of a metallization layer of a substrate. In an embodiment, the metallization layer includes grains of a conductor, wherein a first average grain size and a second average grain size correspond, respectively, to a first sub-layer and a second sub-layer of the metallization layer. The first sub-layer and the second sub-layer each span at least 5% of a thickness of the metallization layer. A difference between the first average grain size and the second average grain size is at least 10% of the first average grain size. In another embodiment, a first condition of metallization processing contributes to grains of the first sub-layer being relatively large, wherein an alternative condition of metallization processing contributes to grains of the second sub-layer being relatively small. A grain size gradient across a thickness of the metallization layer facilitates etching processes being anisotropic.Type: GrantFiled: June 1, 2021Date of Patent: December 13, 2022Assignee: Intel CorporationInventors: Jeremy Ecton, Nicholas Haehn, Oscar Ojeda, Arnab Roy, Timothy White, Suddhasattwa Nad, Hsin-Wei Wang
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Publication number: 20220199453Abstract: Described herein are carrier assemblies, and related devices and methods. In some embodiments, a carrier assembly includes a carrier; a textured material including texturized microstructures coupled to the carrier; and microelectronic components mechanically coupled to the texturized microstructures. In some embodiments, a carrier assembly includes a carrier having a front side and a back side; an electrode on the front side of the carrier; a dielectric material on the electrode; a charging contact on the back side coupled to the electrode; and microelectronic components electrostatically coupled to the front side of the carrier. In some embodiments, a carrier assembly includes a carrier having a front side and a back side; electrodes on the front side; a dielectric material including texturized microstructures on the electrodes; charging contacts on the back side coupled to the plurality of electrodes; and microelectronic components mechanically and electrostatically coupled to the front side of the carrier.Type: ApplicationFiled: December 23, 2020Publication date: June 23, 2022Applicant: Intel CorporationInventors: Michael J. Baker, Shawna M. Liff, Hsin-Wei Wang, Albert S. Lopez
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Publication number: 20220099624Abstract: A nucleic acid detection host includes a host body, a detection kit installation area, a sample heating area, a sampling groove, a heating structure, and an image collection unit. The detection kit installation area is configured to detachably install a nucleic acid detection kit. The sampling groove is disposed on the detection kit installation area and is connected to the detection kit installation area. The heating structure is configured to heat the nucleic acid detection kit to perform a PCR amplification reaction and an electrophoretic detection. The image collection unit is configured to collect an image of the nucleic acid detection kit. A nucleic acid detection device including the nucleic acid detection host is also disclosed. The nucleic acid detection device has a simple structure, which is portable, flexible, and convenient, and can be used at home.Type: ApplicationFiled: September 29, 2021Publication date: March 31, 2022Inventors: CHIA-HSIN CHANG, PO-CHING HUANG, PENG-YU CHIU, CHIEH-CHUNG CHUNG, CHUN-CHIH CHEN, HSIN-WEI WANG
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Publication number: 20210289638Abstract: Techniques and mechanisms for providing anisotropic etching of a metallization layer of a substrate. In an embodiment, the metallization layer includes grains of a conductor, wherein a first average grain size and a second average grain size correspond, respectively, to a first sub-layer and a second sub-layer of the metallization layer. The first sub-layer and the second sub-layer each span at least 5% of a thickness of the metallization layer. A difference between the first average grain size and the second average grain size is at least 10% of the first average grain size. In another embodiment, a first condition of metallization processing contributes to grains of the first sub-layer being relatively large, wherein an alternative condition of metallization processing contributes to grains of the second sub-layer being relatively small. A grain size gradient across a thickness of the metallization layer facilitates etching processes being anisotropic.Type: ApplicationFiled: June 1, 2021Publication date: September 16, 2021Applicant: INTEL CORPORATIONInventors: Jeremy Ecton, Nicholas Haehn, Oscar Ojeda, Arnab Roy, Timothy White, Suddhasattwa Nad, Hsin-Wei Wang
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Publication number: 20210280463Abstract: A conductive route for an integrated circuit assembly may be formed using a sequence of etching and passivation steps through layers of conductive material, wherein the resulting structure may include a first route portion having a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, an etch stop structure on the first route portion, a second route portion on the etch stop layer, wherein the second route portion has a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, and a passivating layer abutting the at least one side surface of the second route portion.Type: ApplicationFiled: March 5, 2020Publication date: September 9, 2021Applicant: INTEL CORPORATIONInventors: Jeremy Ecton, Brandon C. Marin, Leonel Arana, Matthew Tingey, Oscar Ojeda, Hsin-Wei Wang, Suddhasattwa Nad, Srinivas Pietambaram, Gang Duan
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Patent number: 11116084Abstract: Techniques and mechanisms for providing anisotropic etching of a metallization layer of a substrate. In an embodiment, the metallization layer includes grains of a conductor, wherein a first average grain size and a second average grain size correspond, respectively, to a first sub-layer and a second sub-layer of the metallization layer. The first sub-layer and the second sub-layer each span at least 5% of a thickness of the metallization layer. A difference between the first average grain size and the second average grain size is at least 10% of the first average grain size. In another embodiment, a first condition of metallization processing contributes to grains of the first sub-layer being relatively large, wherein an alternative condition of metallization processing contributes to grains of the second sub-layer being relatively small. A grain size gradient across a thickness of the metallization layer facilitates etching processes being anisotropic.Type: GrantFiled: September 27, 2017Date of Patent: September 7, 2021Assignee: Intel CorporationInventors: Jeremy Ecton, Nicholas Haehn, Oscar Ojeda, Arnab Roy, Timothy White, Suddhasattwa Nad, Hsin-Wei Wang
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Publication number: 20210249322Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, a first and second integrated circuit device each having a first surface, a second surface, at least one side extending between the first and second surface, and an edge defined at an intersection of the second surface and the at least one side of each respective integrated circuit device, wherein the first surface of each integrated circuit device is electrically attached to the electronic substrate, an underfill material between the first surface of each integrated circuit device and the electronic substrate, and between the sides of the first and second integrated circuit devices, and at least one barrier structure adjacent at least one of the edge of first integrated circuit device and the edge of the second integrated circuit device, wherein the underfill material abuts the at least one barrier structure.Type: ApplicationFiled: February 11, 2020Publication date: August 12, 2021Applicant: Intel CorporationInventors: Ziyin Lin, Vipul Mehta, Wei Li, Edvin Cetegen, Xavier Brun, Yang Guo, Soud Choudhury, Shan Zhong, Christopher Rumer, Nai-Yuan Liu, Ifeanyi Okafor, Hsin-Wei Wang
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Publication number: 20200236795Abstract: Techniques and mechanisms for providing anisotropic etching of a metallization layer of a substrate. In an embodiment, the metallization layer includes grains of a conductor, wherein a first average grain size and a second average grain size correspond, respectively, to a first sub-layer and a second sub-layer of the metallization layer. The first sub-layer and the second sub-layer each span at least 5% of a thickness of the metallization layer. A difference between the first average grain size and the second average grain size is at least 10% of the first average grain size. In another embodiment, a first condition of metallization processing contributes to grains of the first sub-layer being relatively large, wherein an alternative condition of metallization processing contributes to grains of the second sub-layer being relatively small. A grain size gradient across a thickness of the metallization layer facilitates etching processes being anisotropic.Type: ApplicationFiled: September 27, 2017Publication date: July 23, 2020Applicant: INTEL CORPORATIONInventors: Jeremy Ecton, Nicholas Haehn, Oscar Ojeda, Arnab Roy, Timothy White, Suddhasattwa Nad, Hsin-Wei Wang
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Patent number: 10515824Abstract: A method of anisotropic etching comprises forming a metal layer above a substrate. A mask layer is formed on the metal layer with openings defined in the mask layer to expose portions of the metal layer. The exposed portions of the metal layer are introduced to an active etchant solution that includes nanoparticles as an insoluble banking agent. In further embodiments, the exposed portions of the metal layer are introduced to a magnetic and/or an electrical field.Type: GrantFiled: January 11, 2018Date of Patent: December 24, 2019Assignee: Intel CorporationInventors: Jeremy Ecton, Leonel Arana, Nicholas S. Haehn, Hsin-Wei Wang, Oscar Ojeda, Arnab Roy
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Patent number: 10437299Abstract: An electronic device includes a first housing portion, a second housing portion, a circuit board, a battery, a display screen, and a heat-dissipating structure. The second housing portion is coupled together with the first housing portion. The circuit board and the battery are received within the second housing portion. The heat-dissipating structure is arranged between the circuit board and the display screen. The heat-dissipating structure includes a substrate including a first surface and a second surface opposite to the first surface and defines an opening passing through the first surface and the second surface. The heat dissipating element is located in the opening.Type: GrantFiled: May 25, 2018Date of Patent: October 8, 2019Assignee: Chiun Mai Communication Systems, Inc.Inventors: Hsin-Wei Wang, Chia-Hsin Chang
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Publication number: 20190214272Abstract: A method of anisotropic etching comprises forming a metal layer above a substrate. A mask layer is formed on the metal layer with openings defined in the mask layer to expose portions of the metal layer. The exposed portions of the metal layer are introduced to an active etchant solution that includes nanoparticles as an insoluble banking agent. In further embodiments, the exposed portions of the metal layer are introduced to a magnetic and/or an electrical field.Type: ApplicationFiled: January 11, 2018Publication date: July 11, 2019Inventors: Jeremy ECTON, Leonel ARANA, Nicholas S. HAEHN, Hsin-Wei WANG, Oscar OJEDA, Arnab ROY
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Publication number: 20190004574Abstract: An electronic device includes a first housing portion, a second housing portion, a circuit board, a battery, a display screen, and a heat-dissipating structure. The second housing portion is coupled together with the first housing portion. The circuit board and the battery are received within the second housing portion. The heat-dissipating structure is arranged between the circuit board and the display screen. The heat-dissipating structure includes a substrate including a first surface and a second surface opposite to the first surface and defines an opening passing through the first surface and the second surface. The heat dissipating element is located in the opening.Type: ApplicationFiled: May 25, 2018Publication date: January 3, 2019Inventors: HSIN-WEI WANG, CHIA-HSIN CHANG
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Patent number: 9449163Abstract: A method for logging in to an application program of an electronic device presets a plurality groups of account information of the application program, and presets fingerprints corresponding the plurality of groups of account information in a storage device. When the application program is executed and a user interface of the application program is displayed, the method receives fingerprint data input. When the received fingerprint data matches one of the fingerprints, the method further confirms a group of account information corresponding to the matched fingerprint, and logs in to the application program using the confirmed account information.Type: GrantFiled: October 30, 2014Date of Patent: September 20, 2016Assignee: Chiun Mai Communication Systems, Inc.Inventor: Hsin-Wei Wang