Abstract: A capacitor on a fin structure includes a fin structure. A dielectric layer covers the fin structure. A first electrode extension is embedded within the fin structure. A first electrode penetrates the dielectric layer and contacts the first electrode extension. A second electrode and a capacitor dielectric layer are disposed within the dielectric layer. The capacitor dielectric layer surrounds the second electrode, and the capacitor dielectric layer is between the second electrode and the first electrode extension.

Abstract: An integrated circuit includes a first horizontal conductor and a second horizontal conductor. The integrated circuit includes a first pair of blocks including a first first-type block and a first second-type block, a second pair of blocks including a second first-type block and a second second-type block, and a third pair of blocks including a third first-type block and a third second-type block. The first first-type block and the first second-type block are aligned along a first column. The second first-type block and the second second-type block are aligned along a second column. The third first-type block and the third second-type block are aligned along a third column. The second first-type block is connected to the first second-type block through the second horizontal conductor. The third first-type block is conductively connected to the second second-type block through the first horizontal conductor.

Abstract: In some embodiments, a device is described that includes die components on an upper surface of a redistribution layer interposer to provide a chip on interposer structure. A packaging substrate is present on the chip on interposer structure. A thermal ring is present on the packaging substrate, wherein the thermal ring is positioned about a perimeter of the chip on interposer structure. Molding material is deposited on the packaging substrate in a space between the thermal ring and the chip on interposer structure.

Abstract: One aspect of the present disclosure pertains to a package structure. The package structure includes a die bonded to a substrate; a molding compound over the substrate and surrounding the die; a liquid metal over a top surface of the die; a ring structure over the molding compound and surrounding sidewalls of the liquid metal; and a heat sink attached to the ring structure and contacting the liquid metal. The ring structure includes an inner ring portion interfacing the liquid metal and an outer ring portion supporting the heat sink, and the inner ring portion includes through holes that form circulation channels for the liquid metal.

Abstract: Systems and methods are provided for fail-safe protection of circuitry from electrostatic discharge due through input and output connections. The power circuitry may include a string of diodes, connections to power lines, and particular diodes for voltage pull-up and pull-down clamping. There may be both a pull-up third diode in the diode string for connection between I/O and VDD and a pull-down third diode between I/O and VSS. During an ESD event the ESD device is configured to hold voltage from exceeding a threshold voltage and damaging internal circuitry. During operational mode the ESD device is turned off and does not interfere with circuit operations.

Abstract: A method for treating a micro electro-mechanical system (MEMS) component is disclosed. In one example, the method includes the steps of providing a first wafer, treating the first wafer to form cavities and at least an oxide layer on a top surface of the first wafer using a first chemical vapor deposition (CVD) process, providing a second wafer, bonding the second wafer on a top surface of the at least one oxide layer, treating the second wafer to form a first plurality of structures, depositing a layer of Self-Assembling Monolayer (SAM) to a surface of the MEMS component using a second CVD process.

Abstract: A semiconductor device and methods of forming the same. In some embodiments, a method for forming a semiconductor device includes forming a redistribution layer that includes connecting vias and a surface mount pad via and the top surface width of each via is larger than a bottom surface width. The method includes connecting a component to the redistribution layer by a plurality of ?-bumps and filling a gap between the component and the redistribution layer with a mold and an underfill. The method includes etching back the redistribution layer to expose the surface mount pad via and attaching a surface mount pad to the surface mount pad via. The surface mount pad is connected to the bottom surface width of the surface mount pad via and the surface mount pad includes a protrude. The method includes connecting a device to a bottom surface of the surface mount pad.

Abstract: A package structure is provided. The package structure includes a device die bonded to a package substrate via a plurality of connectors. The package structure includes a dummy die bonded to the package substrate via a plurality of dummy connectors and disposed adjacent to the device die. The dummy die includes a base portion, an upper portion bonded to the base portion, and an edge molding material formed over the base portion and surrounding the upper portion. The package structure also includes a package molding material over the package substrate and around the dummy die and the device die. The Young's modulus of the edge molding material is less than the Young's modulus of the package molding material.

Abstract: An operation method and an operation device for operating a real-time discussion window are provided. The operation method for operating the real-time discussion window includes the following steps. A discussion topic is obtained from an initiator. A participant candidate list is provided. The participant candidate list includes a plurality of non-player characters. A participant suggestion list is provided from the candidate list according to the discussion topic. At least one of the non-player characters is added into the real-time discussion window according to a selection result of the initiator. At least one relevant technical person is invited into the real-time discussion window. The discussion topic is discussed in the real-time discussion window. A discussion report is automatically generated according to the discussion content in the real-time discussion window.

Abstract: A semiconductor package structure according to the present disclosure includes a substrate, an interposer bonded to the substrate by way of a plurality of first type solder features, and an integrated circuit (IC) die bonded to the interposer by way of a plurality of second type solder features. The interposer includes a redistribution structure and a seal ring structure extending around the redistribution structure. At least one of the plurality of second type solder features is electrically coupled to the seal ring structure.

Abstract: A package structure according to the present disclosure includes a package substrate, an interposer bonded to the package substrate, a first die and a second die bonded to the interposer by way of micro bumps, an underfill surrounding the micro bumps, disposed between the first die and the interposer as well as between the second die and the interposer, a metal layer interfacing the interposer, the underfill, sidewalls of the first die, and sidewalls of the second die, a molding material over the metal layer, and a thermal interface material disposed over the molding material, the metal layer, the first die, and the second die.

Abstract: An electronic device is provided. The electronic device includes a first circuit module and a first shield. The first shield is disposed at a lateral side of the circuit module and includes a first opening configured to reduce a parasitic coupling of the first circuit module and the first shield.

Abstract: An execution method and an execution system for a virtual meeting are provided. The execution method includes the following steps. A discussion item is received. The discussion item is compiled into a plurality of tasks. The tasks are distributed to a plurality of virtual agents. At least one analysis information is obtained by at least one of the virtual agents using an industrial data database. The industrial data database is built via an analytic AI model. At least one guidance information is obtained by at least one of the virtual agents using an industrial knowledge database. The industrial knowledge database is built via a generative AI model. If the analysis information and the guidance information meet the predetermined condition, the virtual expert compiles the analysis information and the guidance information into a recommendation report.

Abstract: An execution method and an execution system for a virtual meeting are provided. The execution method includes the following steps. A discussion item is received. The discussion item is compiled into a plurality of tasks. The tasks are distributed to a plurality of virtual agents. At least one analysis information is obtained by at least one of the virtual agents using an industrial data database. The industrial data database is built via an analytic AI model. At least one guidance information is obtained by at least one of the virtual agents using an industrial knowledge database. The industrial knowledge database is built via a generative AI model. If the analysis information and the guidance information meet the predetermined condition, the virtual expert compiles the analysis information and the guidance information into a recommendation report.

Abstract: An integrated circuit includes a first horizontal conductor and a second horizontal conductor. The integrated circuit includes a first diode between a first first-type block and a first second-type block, a second diode between a second first-type block and a second second-type block, and a third diode between a third first-type block and a third second-type block. The first first-type block and the first second-type block are aligned along a first column. The second first-type block and the second second-type block are aligned along a second column. The third first-type block and the third second-type block are aligned along a third column. The second first-type block is connected to the first second-type block through the second horizontal conductor. The third first-type block is conductively connected to the second second-type block through the first horizontal conductor.

Abstract: In general, the subject matter described in this disclosure can be embodied in methods, systems, and program products for operating a display device. A pixel of a the display device is refreshed while the display device is operating at a first refresh rate, including by: turning off emission of the LED; programming a driving transistor that drives the LED; and turning on emission of the LED a first delay of time after the programming of the driving transistor. The pixel of the display device is refreshed while the display device is operating at a second refresh rate, including by: turning off emission of the LED; programming the driving transistor that drives the LED; and turning on emission of the LED a second delay of time after the programming of the driving transistor.

Abstract: A method may include measuring, from a device having a display panel configured to operate at a first refresh rate or a second refresh rate, a difference in luminance of the display panel between the first refresh rate and the second refresh rate for an input gray level. The method may also include applying, based on the measured difference in luminance, a value offset to a default gamma value used by the device for the input gray level when the display panel is operating at the second refresh rate, thereby generating a new gamma value. The method may further include storing, at the device, the new gamma value, where subsequent to the storing, the device is configured to override the default gamma value for the input gray level with the new gamma value when the display panel is operating at the second refresh rate.

Abstract: A method includes forming a first photoresist layer on a dielectric layer; performing a first light-exposure process on the first photoresist layer using a first photolithography mask, wherein during the first light-exposure process, a first region the first photoresist layer is blocked from being exposed, a second region of the first photoresist layer is exposed, and a third region of the first photoresist layer is exposed, wherein the second region encircles the first region and the third region encircles the second region; performing a second light-exposure process on the first photoresist layer using a second photolithography mask, wherein during the second light-exposure process, the first region of the first photoresist layer is exposed, the second region of the first photoresist layer is exposed, and the third region of the first photoresist layer is blocked from being exposed; and developing the first photoresist layer.

Abstract: A method includes forming a thermal layer stack covering a top surface of a package component, wherein the thermal layer stack includes sublayers of different metals; connecting the package component to a package substrate; depositing a molding material on the package substrate and on the package component; and attaching a support ring to the molding material.

Abstract: An electronic system and a semiconductor module is provided. The semiconductor module includes a carrier, a plurality of passive components, an electronic component, and an encapsulation layer. The plurality of passive components is disposed over the carrier. The electronic component is disposed over the carrier and configured to clamp a voltage of the semiconductor module. The encapsulation layer covers and contacts the plurality of passive components and the electronic component.