Patents by Inventor Hsiu-Chieh Cheng

Hsiu-Chieh Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8510254
    Abstract: An engineering analysis tool comprises a unified resource model-based (URM) objective and tool mapping capability for linking engineering analysis objectives to analysis tools. A Markov chain-based analysis plan generator (APTG) for reusing engineering analysis plans may be included in the engineering analysis tool. Further, the engineering analysis tool comprises a graphic symptom capturer (GSC) that auto-captures engineering perceived fault symptoms from engineering data analysis (EDA) tools.
    Type: Grant
    Filed: October 14, 2009
    Date of Patent: August 13, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya-Jung Tsai, Chih-Min Fan, Shi-Chung Chang, Hsiu-Chieh Cheng, Fang-Hsiang Su, Wu-Chi Chen, Ching-Pin Kao
  • Publication number: 20100174396
    Abstract: An engineering analysis tool comprises a unified resource model-based (URM) objective and tool mapping capability for linking engineering analysis objectives to analysis tools. A Markov chain-based analysis plan generator (APTG) for reusing engineering analysis plans may be included in the engineering analysis tool. Further, the engineering analysis tool comprises a graphic symptom capturer (GSC) that auto-captures engineering perceived fault symptoms from engineering data analysis (EDA) tools.
    Type: Application
    Filed: October 14, 2009
    Publication date: July 8, 2010
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya-Jung Tsai, Chih-Min Fan, Shi-Chung Chang, Hsiu-Chieh Cheng, Fang-Hsiang Su, Wu-Chi Chen, Ching-Pin Kao
  • Patent number: 6593220
    Abstract: A new method is provided for the creation of a solder mask for solder bump formation. A passivation layer is deposited on the semiconductor surface in the surface of which a contact pad has been provided, an opening is created in the layer of passivation that partially exposed the surface of the contact pad. A layer of UBM metal is deposited and patterned, limiting the layer of UBM to overlying and contacting the contact pad of the solder bump. A layer of elastomer is blanket deposited over the surface and patterned, creating an opening overlying the opening created in the layer of passivation, exposing the layer of UBM. The exposed surface of the layer of UBM is electroplated with a layer of solder, using the opening created in the layer of elastomer as the self-aligned electroplating opening. A step of reflow of the electroplated solder and the layer of elastomer completes the process of the invention, creating a solder bump surrounded by a layer of cured elastomer.
    Type: Grant
    Filed: January 3, 2002
    Date of Patent: July 15, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Hsiu-Mei Yu, Ken-Shen Chou, Hsiu-Chieh Cheng, Shun-Liang Hsu