Abstract: A device for accessing a memory includes a memory module, a CPU and a north bridge chipset. The memory module has an ordinary area and a redundant area. The CPU outputs redundant address data. The north bridge chipset includes a memory module controller, a data register and a pointer. The pointer records the redundant address data. When a writing procedure is performed, the data register records to-be-stored data, and the memory module controller stores the to-be-stored data to a first physical address of the redundant area according to the pointer and the data register. In addition, when a reading procedure is performed, the data register records a to-be-read amount, and the memory module controller reads to-be-read data from a second physical address of the redundant area according to the pointer and the data register.

Abstract: A motherboard includes a south-bridge chipset, a north-bridge chipset and a central processor unit (CPU). The south-bridge chipset generates at least control-setting data. The north-bridge chipset has a reset register for controlling the north-bridge chipset to generate a reset signal and a control-set resister for storing the control-setting data generated by the south-bridge chipset. The CPU has a plurality of configuration parameters. The configuration parameters of the CPU are reset in accordance with the reset signal, and the control-setting data is written into the CPU by the north-bridge chipset to set one of the configuration parameters of the CPU.

Abstract: A device for burst reading/writing memory data includes a memory module and a north bridge chipset. The device is used for executing a power on self test (POST). The memory module has a plurality of memory cells and the north bridge chipset includes a programmable register module and a memory module controller, wherein the programmable register module stores at least one set of default information. The memory module controller performing burst read/write on the memory cells according to the default information stored in the programmable register module.

Abstract: A device for DRAM initialization of a computer system. A detection circuit detects memory condition and outputs a fast initialization signal. A buffer stores initialization parameters of the memory. A memory controller sets the initialization parameters according to memory information, and reads the memory condition to initialize the memory when booting and receiving the fast initialization signal.