Patents by Inventor Hsiu-Chuan Chu

Hsiu-Chuan Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6989337
    Abstract: A silicon oxide gap-filling process is described, wherein a CVD process having an etching effect is performed to fill up a trench with silicon oxide. The reaction gases used in the CVD process include deposition gases and He/H2 mixed gas as a sputtering-etching gas, wherein the percentage of the He/H2 mixed gas in the total reaction gases is raised with the increase of the aspect ratio of the trench.
    Type: Grant
    Filed: October 2, 2003
    Date of Patent: January 24, 2006
    Assignee: United Microelectric Corp.
    Inventors: Hsiu-Chuan Chu, Chih-An Huang, Teng-Chun Tsai, Neng-Kuo Chen
  • Publication number: 20050159007
    Abstract: A manufacturing method of shallow trench isolation (STI) structure is described. A substrate is provided, wherein a patterned pad oxide layer and a mask layer are formed on the substrate, and at least a trench is formed in the substrate, wherein the trench is formed by exposing a portion of the pad oxide layer and the mask layer. Then, a liner layer on a surface of the trench is formed. A high density plasma chemical vapor deposition (HDP-CVD) process is performed to form an isolation layer on the substrate and over the trench, wherein the trench is at least filled with the isolation layer. The HDP-CVD process includes a first stage process and a second stage process. The bias power of the second stage process is larger than the bias power of the first stage process. Thereafter, the isolation layer over the trench, the mask layer and the pad oxide layer are removed sequentially.
    Type: Application
    Filed: January 21, 2004
    Publication date: July 21, 2005
    Inventors: Neng-Kuo Chen, Teng-Chun Tsai, Hsiu-Chuan Chu, Chih-An Huang
  • Patent number: 6913978
    Abstract: A method of fabricating a shallow trench isolation structure is disclosed. On a substrate, a pad oxide layer and a mask layer are successively formed. The pad oxide layer, the mask layer and a portion of the substrate are patterned to form a trench. After performing a rapid wet thermal process, a liner layer is formed on the exposed surface of the substrate, including the exposed silicon surface of the substrate in the trench and sidewalls and the surface of the mask layer. An oxide layer is deposited over the trench and the substrate and fills the trench. A planarization process is performed until the mask layer is exposed. The mask layer and the pad oxide layer are removed to complete the shallow trench isolation structure.
    Type: Grant
    Filed: February 25, 2004
    Date of Patent: July 5, 2005
    Assignee: United Microelectronics Corp.
    Inventors: Neng-Kuo Chen, Hsiu-Chuan Chu, Chih-An Huang, Hsiao-Ling Lu, Teng-Chun Tsai
  • Publication number: 20050074946
    Abstract: A silicon oxide gap-filling process is described, wherein a CVD process having an etching effect is performed to fill up a trench with silicon oxide. The reaction gases used in the CVD process include deposition gases and He/H2 mixed gas as a sputtering-etching gas, wherein the percentage of the He/H2 mixed gas in the total reaction gases is raised with the increase of the aspect ratio of the trench.
    Type: Application
    Filed: October 2, 2003
    Publication date: April 7, 2005
    Inventors: Hsiu-Chuan Chu, Chih-An Huang, Teng-Chun Tsai, Neng-Kuo Chen