Patents by Inventor Hsiu-Chuan Shu

Hsiu-Chuan Shu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • THROUGH-SILICON VIA IN INTEGRATED CIRCUIT PACKAGING
    Publication number: 20230205967
    Abstract: The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.
    Type: Application
    Filed: February 17, 2023
    Publication date: June 29, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fong-yuan CHANG, Chin-Chou LIU, Chin-Her CHIEN, Cheng-Hung YEH, Po-Hsiang HUANG, Sen-Bor JAN, Yi-Kan CHENG, Hsiu-Chuan SHU
  • Through-silicon vias in integrated circuit packaging
    Patent number: 11586797
    Abstract: The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: February 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fong-yuan Chang, Chin-Chou Liu, Chin-Her Chien, Cheng-Hung Yeh, Po-Hsiang Huang, Sen-Bor Jan, Yi-Kan Cheng, Hsiu-Chuan Shu
  • Through-Silicon Vias in Integrated Circuit Packaging
    Publication number: 20210173998
    Abstract: The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.
    Type: Application
    Filed: February 19, 2021
    Publication date: June 10, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fong-yuan CHANG, Chin-Chou LIU, Chin-Her CHIEN, Cheng-Hung YEH, Po-Hsiang HUANG, Sen-Bor JAN, Yi-Kan CHENG, Hsiu-Chuan SHU
  • Through-silicon vias in integrated circuit packaging
    Patent number: 10949597
    Abstract: The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: March 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fong-yuan Chang, Chin-Chou Liu, Chin-Her Chien, Cheng-Hung Yeh, Po-Hsiang Huang, Sen-Bor Jan, Yi-Kan Cheng, Hsiu-Chuan Shu
  • THROUGH-SILICON VIAS IN INTEGRATED CIRCUIT PACKAGING
    Publication number: 20200019668
    Abstract: The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.
    Type: Application
    Filed: July 2, 2019
    Publication date: January 16, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fong-yuan CHANG, Chin-Chou Liu, Chin-Her CHIEN, Cheng-Hung YEH, Po-Hsiang HUANG, Sen-Bor Jan, Yi-Kan Cheng, Hsiu-Chuan Shu
  • Method of fabricating a recess channel transistor
    Patent number: 7531438
    Abstract: A method of fabricating a recess channel transistor is provided. First, a hard mask is formed on a doped-semiconductor layer and a substrate. The doped-semiconductor layer and the substrate are etched to form a trench and define a source/drain in the doped-semiconductor layer. An implantation process is performed with a tilt angle on sidewalls of the trench to form an implant area. A thermal oxidation process is performed to form an oxide layer. The oxide layer comprises a first thickness on the source/drain in the sidewalls of the trench and a second thickness on the other portion in the sidewalls of the trench.
    Type: Grant
    Filed: July 24, 2006
    Date of Patent: May 12, 2009
    Assignee: ProMOS Technologies Inc.
    Inventors: Jih-Wen Chou, Chih-Hsun Chu, Hsiu-Chuan Shu
  • Method of fabricating a recess channel transistor
    Publication number: 20070249123
    Abstract: A method of fabricating a recess channel transistor is provided. First, a hard mask is formed on a doped-semiconductor layer and a substrate. The doped-semiconductor layer and the substrate are etched to form a trench and define a source/drain in the doped-semiconductor layer. An implantation process is performed with a tilt angle on sidewalls of the trench to form an implant area. A thermal oxidation process is performed to form an oxide layer. The oxide layer comprises a first thickness on the source/drain in the sidewalls of the trench and a second thickness on the other portion in the sidewalls of the trench.
    Type: Application
    Filed: July 24, 2006
    Publication date: October 25, 2007
    Inventors: Jih-Wen Chou, Chih-Hsun Chu, Hsiu-Chuan Shu