Patents by Inventor Hsiu-Chun Lee
Hsiu-Chun Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9985105Abstract: The invention provides a method for fabricating a semiconductor device, including: forming a dummy gate on a substrate, forming an inter-layer dielectric layer (ILD) on the dummy gate and the substrate, forming a metal layer on the upper surface of the dummy gate, removing the dummy gate to form a trench in the inter-layer dielectric layer (ILD), conformally forming a gate dielectric layer in the trench, conformally forming a first conductive type metal layer on the gate dielectric layer, anisotropic etching the first conductive type metal layer and the gate dielectric layer over the metal layer to form a gap in the inter-layer dielectric layer (ILD), and filling a second conductive type metal layer in the gap.Type: GrantFiled: June 30, 2016Date of Patent: May 29, 2018Assignee: Nanya Technology CorporationInventors: Shin-Yu Nieh, Tieh-Chiang Wu, Wei-Ming Liao, Jei-Cheng Huang, Hai-Han Hung, Hsiu-Chun Lee
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Publication number: 20160351678Abstract: The invention provides a method for fabricating a semiconductor device, including: forming a dummy gate on a substrate, forming an inter-layer dielectric layer (ILD) on the dummy gate and the substrate, forming a metal layer on the upper surface of the dummy gate, removing the dummy gate to form a trench in the inter-layer dielectric layer (ILD), conformally forming a gate dielectric layer in the trench, conformally forming a first conductive type metal layer on the gate dielectric layer, anisotropic etching the first conductive type metal layer and the gate dielectric layer over the metal layer to form a gap in the inter-layer dielectric layer (ILD), and filling a second conductive type metal layer in the gap.Type: ApplicationFiled: June 30, 2016Publication date: December 1, 2016Inventors: Shin-Yu Nieh, Tieh-Chiang Wu, Wei-Ming Liao, Jei-Cheng Huang, Hai-Han Hung, Hsiu-Chun Lee
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Publication number: 20140264640Abstract: The invention provides a semiconductor device, including: a substrate; a U-shaped gate dielectric layer formed on the substrate; and a dual work function metal gate layer on the inner surface of U-shaped gate dielectric layer, wherein the dual work function metal gate layer includes a first conductive type metal layer and a second conductive type metal layer.Type: ApplicationFiled: March 18, 2013Publication date: September 18, 2014Applicant: NANYA TECHNOLOGY CORP.Inventors: Shin-Yu Nieh, Tieh-Chiang Wu, Wei-Ming Liao, Jei-Cheng Huang, Hai-Han Hung, Hsiu-Chun Lee
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Patent number: 8377632Abstract: The present invention provides a method of reducing microloading effect by using a photoresist layer as a buffer. The method includes: providing a substrate defined with a dense region and an isolated region. Then, a dense feature pattern and an isolated feature pattern are formed on the dense region and the isolated region respectively. After that, a photoresist layer is formed to cover the isolated region. Finally, the substrate and the photoresist layer are etched by taking the dense feature pattern and the isolated feature pattern as a mask.Type: GrantFiled: May 29, 2011Date of Patent: February 19, 2013Assignee: Nanya Technology Corp.Inventors: Hsiu-Chun Lee, Yi-Nan Chen, Hsien-Wen Liu
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Publication number: 20120305525Abstract: A method of reducing striation on a sidewall of a recess is provided. The method includes the steps of providing a substrate covered with a photoresist layer. Then, the photoresist layer is etched to form a patterned photoresist layer. Later, a repairing process is performed by treating the patterned photoresist layer with a repairing gas which is selected from the group consisting of CF4, HBr, O2 and He. Next, the substrate is etched by taking the patterned photoresist layer as a mask after the repairing process. Finally, the patterned photoresist layer is removed.Type: ApplicationFiled: May 31, 2011Publication date: December 6, 2012Inventors: Hsiu-Chun Lee, Yi-Nan Chen, Hsien-Wen Liu
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Publication number: 20120302030Abstract: A method of fabricating a deep trench capacitor includes the steps as follows. Firstly, a substrate having a trench therein is provided. Then, a bottom electrode is formed in the substrate around the trench. Later, a capacitor dielectric layer is formed to surround an inner sidewall of the trench. After that, a first conductive layer is form to fill up the trench. Subsequently, a material layer is formed on the substrate. Later, a hole is formed in the material layer, wherein the hole is directly above the trench. Finally, a second conductive layer is form to fill in the hole.Type: ApplicationFiled: May 29, 2011Publication date: November 29, 2012Inventors: Hsiu-Chun Lee, Yi-Nan Chen, Hsien-Wen Liu
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Publication number: 20120301833Abstract: The present invention provides a method of reducing microloading effect by using a photoresist layer as a buffer. The method includes: providing a substrate defined with a dense region and an isolated region. Then, a dense feature pattern and an isolated feature pattern are formed on the dense region and the isolated region respectively. After that, a photoresist layer is formed to cover the isolated region. Finally, the substrate and the photoresist layer are etched by taking the dense feature pattern and the isolated feature pattern as a mask.Type: ApplicationFiled: May 29, 2011Publication date: November 29, 2012Inventors: Hsiu-Chun Lee, Yi-Nan Chen, Hsien-Wen Liu
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Patent number: 8252684Abstract: A method of forming a trench by a silicon-containing mask is provided in the present invention. The method includes providing a substrate covered with a silicon-containing mask. Then, anti-etch dopants are implanted into the silicon-containing mask to transform the silicon-containing mask into an etching resist mask. Later, the substrate and the etching resist mask are patterned to form at least one trench. Next, a silicon-containing layer is formed to fill into the trench. Finally, the silicon-containing layer is etched by taking the etching resist mask as a mask.Type: GrantFiled: May 30, 2011Date of Patent: August 28, 2012Assignee: Nanya Technology Corp.Inventors: Hsiu-Chun Lee, Yi-Nan Chen, Hsien-Wen Liu
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Patent number: 7569451Abstract: A method of fabricating an isolation shallow trench contains providing a substrate with at least a deep trench, forming a cap layer on the upper portion of the deep trench, forming a crust layer on a portion of the cap layer, defining a trench extending through the cap layer and the conductive layer, and forming an isolation layer in the shallow trench.Type: GrantFiled: January 6, 2008Date of Patent: August 4, 2009Assignee: Nanya Technology Corp.Inventors: Jen-Jui Huang, Hsiu-Chun Lee, Chang-Ho Yeh
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Publication number: 20080286935Abstract: A method of fabricating an isolation shallow trench contains providing a substrate with at least a deep trench, forming a cap layer on the upper portion of the deep trench, forming a crust layer on a portion of the cap layer, defining a trench extending through the cap layer and the conductive layer, and forming an isolation layer in the shallow trench.Type: ApplicationFiled: January 6, 2008Publication date: November 20, 2008Inventors: Jen-Jui Huang, Hsiu-Chun Lee, Chang-Ho Yeh
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Publication number: 20060154435Abstract: A method of fabricating trench isolation for trench-capacitor DRAM devices. After the formation of deep trench capacitors, an isolation trench is etched into a substrate. The isolation trench is initially filled with a first insulating layer, which is then recessed into the isolation trench to a depth that is lower than the substrate main surface. An epitaxial layer is grown from the exposed sidewalls of the isolation trench. The isolation trench is then filled with a second insulating layer.Type: ApplicationFiled: March 20, 2005Publication date: July 13, 2006Inventors: Hsiu-Chun Lee, Tse-Yao Huang, Yinan Chen
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Patent number: 6974741Abstract: Disclosed is a method for forming a shallow trench. The method of the present invention comprises steps of providing a substrate; forming a plurality of operation layers on the substrate; forming photoresist on the uppermost one of the operation layers to define a position to be etched; etching a portion of the operation layers at said position to form an opening; forming a spacing layer on the sidewall of the opening; and etching a portion of the substrate corresponding to the opening to form a shallow trench. By the etching method of the present invention, a striation phenomenon caused by the common mask etch is avoided.Type: GrantFiled: January 6, 2004Date of Patent: December 13, 2005Assignee: NANYA Technology CorporatiionInventors: Hsiu-Chun Lee, Tse-Yao Huang, Yi-Nan Chen
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Publication number: 20050148152Abstract: Disclosed is a method for forming a shallow trench. The method of the present invention comprises steps of providing a substrate; forming a plurality of operation layers on the substrate; forming photoresist on the uppermost one of the operation layers to define a position to be etched; etching a portion of the operation layers at said position to form an opening; forming a spacing layer on the sidewall of the opening; and etching a portion of the substrate corresponding to the opening to form a shallow trench. By the etching method of the present invention, a striation phenomenon caused by the common mask etch is avoided.Type: ApplicationFiled: January 6, 2004Publication date: July 7, 2005Applicant: Nanya Technology CorporationInventors: Hsiu-Chun Lee, Tse-Yao Huang, Yi-Nan Chen
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Publication number: 20050147926Abstract: Disclosed is a method for processing photoresist. The method of the present invention performs Ar plasma process to the photoresist after or before the photoreisist is formed into a pattern to make the photoresist dense.Type: ApplicationFiled: January 2, 2004Publication date: July 7, 2005Applicant: Nanya Technology CorporationInventors: Hsiu-Chun Lee, Tse-Yao Huang, Yi-Nan Chen, Chih-Ta Wang
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Publication number: 20050118531Abstract: A method for controlling line width critical dimension is disclosed. A semiconductor layer is deposited on a substrate. A cap layer is formed on the semiconductor layer. A patterned photoresist is formed on the cap layer. The patterned photoresist has a top surface and vertical sidewalls. A silicon thin film is selectively sputtered on the top surface and vertical sidewalls of the patterned photoresist, but not on the cap layer. The silicon thin film, which has a thickness: x above the top surface and a thickness: y on the sidewalls of the patterned photoresist, wherein xx<, is used to protect the patterned photoresist. Using the silicon thin film and the patterned photoresist as an etching mask, the cap layer is anisotropically etched thereby transferring the photoresists pattern to the cap layer. Finally, using the cap layer as an etching mask, the semiconductor layer is etched.Type: ApplicationFiled: December 2, 2003Publication date: June 2, 2005Inventors: Hsiu-Chun Lee, Tse-Yao Huang, Yi-Nan Chen