Abstract: A mold for manufacturing an LED mounting substrate includes a first molding die and a second molding die, The second molding die covers the first molding die. The second molding die includes a material holding tank, a pressing part and a material inlet channel. The pressing part is protruded on the material holding tank. The pressing part expands along a direction from the first molding die to the second molding die. The material inlet channel is connected between an outer wall of the second molding die and the material holding tank. The material inlet channel shrinks along a direction from the first molding die to the second molding die.

Abstract: An LED mounting substrate includes a lead frame, a base, and a residue of injection molding material. The base is placed on the lead frame, and includes a cavity. The bottom of the cavity includes an opening for exposing portion of the lead frame. The cross-sectional area of the cavity increases along the direction from the lead frame to the top surface of the base. The residue of injection molding material is remained on one of outer walls of the base surrounding the cavity. The cross-sectional area of the residue of injection molding material decreases along the direction from the lead frame to the top surface of the base.

Abstract: An LED mounting substrate includes a lead frame, a base, and a residue of injection molding material. The base is placed on the lead frame, and includes a cavity. The bottom of the cavity includes an opening for exposing portion of the lead frame. The cross-sectional area of the cavity increases along the direction from the lead frame to the top surface of the base. The residue of injection molding material is remained on one of outer walls of the base surrounding the cavity. The cross-sectional area of the residue of injection molding material decreases along the direction from the lead frame to the top surface of the base.

Abstract: A method of forming a misalignment immune antifuse is presented comprised of the following steps. A partially processed semiconductor wafer is provided, containing at least one device electrically connected to a conducting region extending almost to the wafer surface, where the conducting region is surrounded by a dielectric layer which reaches the wafer surface. A blanket layer of amorphous silicon is deposited followed by deposition of a thin blanket layer of TiN and these layers are etched down to the dielectric surface except for that above the conducting region and some of the surrounding dielectric. A thin native oxide is formed over the exposed surface of the amorphous silicon. This is followed by deposition of a thicker TIN layer and of a metallization layer, which are patterned and etched so that contact is made to the lower layers. The oxidation step is repeated so as to oxidize any amorphous silicon surface that may have been inadvertently exposed in the last etching step.