Patents by Inventor Hsiu-Hsien Ting

Hsiu-Hsien Ting has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11387813
    Abstract: A frequency multiplier and a delay-reused duty cycle calibration method thereof are provided. The frequency multiplier includes a first calibration circuit, a second calibration circuit and a controller. In a calibration mode of the frequency multiplier, an output terminal of a delay cell is coupled to an input terminal of the delay cell. The first calibration circuit repeatedly uses the delay cell M times for generating a first delayed signal. The controller controls the delay cell according to the first delayed signal, to find a delay of the delay cell which makes M times the delay be equal to one cycle period of an input clock signal. After the delay is found, the delay cell is repeatedly used M/2 times for generating a second delayed signal. The controller controls the second calibration circuit according to the second delayed signal to make an input calibration signal have a target duty cycle.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: July 12, 2022
    Assignee: MEDIATEK INC.
    Inventors: Hsiu-Hsien Ting, Po-Chun Huang, Yu-Li Hsueh
  • Publication number: 20220069809
    Abstract: A frequency multiplier and a delay-reused duty cycle calibration method thereof are provided. The frequency multiplier includes a first calibration circuit, a second calibration circuit and a controller. In a calibration mode of the frequency multiplier, an output terminal of a delay cell is coupled to an input terminal of the delay cell. The first calibration circuit repeatedly uses the delay cell M times for generating a first delayed signal. The controller controls the delay cell according to the first delayed signal, to find a delay of the delay cell which makes M times the delay be equal to one cycle period of an input clock signal. After the delay is found, the delay cell is repeatedly used M/2 times for generating a second delayed signal. The controller controls the second calibration circuit according to the second delayed signal to make an input calibration signal have a target duty cycle.
    Type: Application
    Filed: April 26, 2021
    Publication date: March 3, 2022
    Inventors: Hsiu-Hsien Ting, Po-Chun Huang, Yu-Li Hsueh