Patents by Inventor Hsiu-Hsing Hsu

Hsiu-Hsing Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Image scaling circuit and method thereof
    Patent number: 7667718
    Abstract: An image scaling circuit and a method for scaling an image into images with different ratios are provided. The image scaling circuit includes a line buffer memory apparatus, a line buffer control apparatus, a first and a second scaling circuit. The first scaling circuit is coupled to the line buffer memory apparatus, and performs a first image scaling interpolation operation on the data output by the line buffer memory apparatus. The second scaling circuit is coupled to the line buffer memory apparatus, and performs a second image scaling interpolation operation on the data output by the line buffer memory apparatus. The line buffer control apparatus is coupled to the line buffer memory apparatus, the first scaling circuit and the second scaling circuit, for controlling the line buffer memory apparatus to receive or output a scan line data according to the operation status of the first and second scaling circuits.
    Type: Grant
    Filed: November 14, 2006
    Date of Patent: February 23, 2010
    Assignee: Novatek Microelectronics Corp.
    Inventors: Hsiu-Hsing Hsu, Min-Hui Chu
  • IMAGE SCALING CIRCUIT AND METHOD THEREOF
    Publication number: 20080122872
    Abstract: An image scaling circuit and a method for scaling an image into images with different ratios are provided. The image scaling circuit includes a line buffer memory apparatus, a line buffer control apparatus, a first and a second scaling circuit. The first scaling circuit is coupled to the line buffer memory apparatus, and performs a first image scaling interpolation operation on the data output by the line buffer memory apparatus. The second scaling circuit is coupled to the line buffer memory apparatus, and performs a second image scaling interpolation operation on the data output by the line buffer memory apparatus. The line buffer control apparatus is coupled to the line buffer memory apparatus, the first scaling circuit and the second scaling circuit, for controlling the line buffer memory apparatus to receive or output a scan line data according to the operation status of the first and second scaling circuits.
    Type: Application
    Filed: November 14, 2006
    Publication date: May 29, 2008
    Applicant: Novatek Microelectronics Corp.
    Inventors: Hsiu-Hsing Hsu, Min-Hui Chu