Abstract: A non-fullerene acceptor polymer includes a structure represented by formula (I). Formula (I) is defined as in the specification. The non-fullerene acceptor polymer has an electron donating unit and an electron attracting end group. The non-fullerene acceptor polymer uses phenyl or its derivatives as the linker to form the polymer.

Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.

Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.

Abstract: A method of forming a semiconductor device includes forming source/drain regions on opposing sides of a gate structure, where the gate structure is over a fin and surrounded by a first dielectric layer; forming openings in the first dielectric layer to expose the source/drain regions; selectively forming silicide regions in the openings on the source/drain regions using a plasma-enhanced chemical vapor deposition (PECVD) process; and filling the openings with an electrically conductive material.

Abstract: Smart rings and methods of manufacturing smart rings are provided. A foundation component of a smart ring, in accordance with one implementations, includes a band having at least an outer surface and an inner surface. The inner surface of the band includes features configured to support electronic components. The foundation component also includes a decorative element having a bottom surface substantially corresponding to a shape of a portion of the outer surface of the band. Furthermore, the decorative element is attached to the outer surface of the band. The action of attaching the decorative element may occur after a band polishing process and before electronic components are attached to the smart ring.

Abstract: Smart rings and methods of manufacturing smart rings are provided. A waterproof design and method of manufacturing of a smart ring, in accordance with one implementation, includes a band having at least an outer surface and an inner surface. The inner surface of the band includes features configured to support electronic components. The waterproofing design and method of manufacturing includes a laser etching a portion of the inner surface and subsequent to the laser etching of the portion, applying an epoxy over the electronic components and over the laser etched portion of the inner surface. Prior to the laser etching, forming an edge rib on the portion of the inner surface, wherein the laser etching is subsequently on the edge rib. Furthermore, the laser etched portion includes an increased contact area for bonding with the epoxy for the waterproof design.

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate, where a top portion of the fin comprises a layer stack that includes alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin; forming openings in the fin on opposing sides of the dummy gate structure; forming source/drain regions in the openings; removing the dummy gate structure to expose the first semiconductor material and the second semiconductor material under the dummy gate structure; performing a first etching process to selectively remove the exposed first semiconductor material, where after the first etching process, the exposed second semiconductor material form nanostructures, where each of the nanostructures has a first shape; and after the first etching process, performing a second etching process to reshape each of the nanostructures into a second shape different from the first shape.

Abstract: A container feeding device includes a casing and first and second latch members. The casing defines a lower retaining space for receiving a plurality of containers that are stacked on one another. The first latch member is operable to enter the lower retaining space for supporting a bottommost container, or leave the lower retaining space to release the bottommost container. The second latch member enters the lower retaining space to support a second bottommost container when the bottommost container is released by the first latch member.

Abstract: A tool set includes a tool holder, a tool and a tool rack. The tool has a groove unit. The tool holder has a latch unit that engages the groove unit. The tool rack includes a rack body and a blocking member. When the tool holder is moved away from the rack body after the tool is moved into the rack body by the tool holder and after the blocking member moves to a blocking position, the tool is blocked by the blocking member so that the latch unit is separated from the groove unit and that the tool holder is separated from the tool.

Abstract: A memory structure including a substrate, a first doped region, a second doped region, a first gate, a second gate, a first charge storage structure, and a second charge storage structure is provided. The first gate is located on the first doped region. The second gate is located on the second doped region. The first charge storage structure is located between the first gate and the first doped region. The first charge storage structure includes a first tunneling dielectric layer, a first dielectric layer, and a first charge storage layer. The second charge storage structure is located between the second gate and the second doped region. The second charge storage structure includes a second tunneling dielectric layer, a second dielectric layer, and a second charge storage layer. The thickness of the second tunneling dielectric layer is greater than the thickness of the first tunneling dielectric layer.

Abstract: A mounting frame for being mounted with either one of first and second screwdrivers, includes a main frame, a mounting seat, and first and second mounting plates. The mounting seat has a plate attachment hole set. The first mounting plate has a first seat attachment hole set operable to be connected to the plate attachment hole set, and a first driver attachment hole set for the first screwdriver to be attached thereto. The second mounting plate has a second seat attachment hole set operable to be connected to the plate attachment hole set, and a second driver attachment hole set for the second screwdriver to be attached thereto.

Abstract: Disclosed herein are system, method, and computer program product embodiments for reducing GPU load by programmatically controlling shading rates in computer graphics. GPU load may be reduced by applying different shading rates to different screen regions. By reading the depth buffer of previous frames and performing image processing, thresholds may be calculated that control the shading rates. The approach may be run on any platform that supports VRS hardware and primitive- or image-based VRS. The approach may be applied on a graphics driver installed on a client device, in a firmware layer between hardware and a driver, in a software layer between a driver and an application, or in hardware on the client device. The approach is flexible and adaptable and calculates and sets the variable rate shading based on the graphics generated by an application without requiring the application developer to manually set variable rate shading.

Abstract: The method of forming the semiconductor structure includes the following steps. First trenches and second trenches are respectively formed in a substrate of the logic region and the substrate of the array region. A dielectric liner is formed in the first trenches and second trenches. First coating blocks and second coating blocks are respectively formed in the first trenches and second trenches. A cap layer is formed on the first coating blocks and the second coating blocks. Oxide structures are formed on the cap layer. Part of the oxide structures and part of the cap layer is removed. A semiconductor layer is formed in the array region and disposed on the substrate and between the oxide structures.

Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.

Abstract: An optoelectronic package and a method for producing the optoelectronic package are provided. The optoelectronic package includes a carrier, a photonic device, a first encapsulant and a second encapsulant. The photonic device is disposed on the carrier. The first encapsulant covers the carrier and is disposed around the photonic device. The second encapsulant covers the first encapsulant and the photonic device. The first encapsulant has a topmost position and a bottommost position, and the topmost position is not higher than a surface of the photonic device.

Abstract: The present disclosure provides a shaft seal device. The shaft seal device includes a main body. The main body includes a channel, a first ring part, a second ring part, a liquid flow hole and a diversion structure. The channel passes through the main body, and includes a channel inner peripheral surface. The first ring part and the second ring part are formed on the channel inner peripheral surface. An aperture of the first ring part is greater than an aperture of the second ring part. The liquid flow hole passes through the main body from an outer surface of the main body to a first inner peripheral surface of the first ring part. The diversion structure is disposed on the first inner peripheral surface and is adjacent to the liquid flow hole.

Abstract: An intellectual quality management method is disclosed. A heatmap risk interface is created according to the required data and the parameter configuration which are calculated using a time dependent risk priority number (RPN) equation. An intellectual audit scheduling algorithm is defined via the heatmap risk interface to automatically generate at least one audit plan. An audit program corresponding to the audit plan is performed and a plurality of problem points are selected. Intellectual root cause category recommendation is performed to the questions points. intellectual corrective actions and preventive action recommendations are performed to the problem points according to the intellectual root cause category recommendation to obtain at least one optimum corrective action and at least one preventive action.

Abstract: A semiconductor device package and a method for manufacturing a semiconductor device package are provided. The semiconductor device package includes a substrate, a clip, and a support structure. The clip is disposed on the substrate. The clip includes a first portion and a second portion separated from each other by a slit. The support structure is above the substrate and supports the clip. The support structure has a first surface and a second surface facing the first surface, and the first surface and the second surface define a gap.

Abstract: An intellectual quality management method is disclosed. A heatmap risk interface is created according to the required data and the parameter configuration which are calculated using a time dependent risk priority number (RPN) equation. An intellectual audit scheduling algorithm is defined via the heatmap risk interface to automatically generate at least one audit plan. An audit program corresponding to the audit plan is performed and a plurality of problem points are selected. Intellectual root cause category recommendation is performed to the questions points. intellectual corrective actions and preventive action recommendations are performed to the problem points according to the intellectual root cause category recommendation to obtain at least one optimum corrective action and at least one preventive action.

Abstract: An intellectual quality management method is disclosed. A heatmap risk interface is created according to the required data and the parameter configuration which are calculated using a time dependent risk priority number (RPN) equation. An intellectual audit scheduling algorithm is defined via the heatmap risk interface to automatically generate at least one audit plan. An audit program corresponding to the audit plan is performed and a plurality of problem points are selected. Intellectual root cause category recommendation is performed to the questions points. intellectual corrective actions and preventive action recommendations are performed to the problem points according to the intellectual root cause category recommendation to obtain at least one optimum corrective action and at least one preventive action.