Abstract: A computing system may implement a basic input/output system (BIOS) update method. The BIOS also includes identifying an installed central processing unit (CPU) of a computer system coupled to a BIOS chipset, selecting CPU firmware corresponding to the installed CPU from a plurality of CPU platform firmware stored on a first memory, and loading the CPU firmware into a shared portion of a second memory coupled to the BIOS chipset, where the shared portion of the second memory is configured to store the CPU firmware as secondary CPU firmware.

Abstract: A computing system may implement a basic input/output system (BIOS) update method. The BIOS also includes identifying an installed central processing unit (CPU) of a computer system coupled to a BIOS chipset, selecting CPU firmware corresponding to the installed CPU from a plurality of CPU platform firmware stored on a first memory, and loading the CPU firmware into a shared portion of a second memory coupled to the BIOS chipset, where the shared portion of the second memory is configured to store the CPU firmware as secondary CPU firmware.

Abstract: In the described embodiments, a computing device executes firmware to perform a startup initialization operation, wherein performing the startup initialization operation comprises setting an operating state of a memory in the computing device to a default low performance memory operating state. After completing the startup initialization operation, the computing device executes an operating system, wherein executing the operating system comprises performing a memory test to determine a high performance memory operating state. The computing device then sets one or more memory configuration values based on the high performance memory operating state, the one or more memory configuration values controlling the operation of the memory.

Abstract: In the described embodiments, a computing device executes firmware to perform a startup initialization operation, wherein performing the startup initialization operation comprises setting an operating state of a memory in the computing device to a default low performance memory operating state. After completing the startup initialization operation, the computing device executes an operating system, wherein executing the operating system comprises performing a memory test to determine a high performance memory operating state. The computing device then sets one or more memory configuration values based on the high performance memory operating state, the one or more memory configuration values controlling the operation of the memory.

Abstract: A frequency working between the north bridge chip and random access memory of a computer system is dynamically and automatically adjusted in response to the frequency change of the CPU, in response to the workload of the north bridge chip or in response to the change of settings in a software program. The computer system may need to perform POST (Power-On Self Test) of BIOS to detect and calibrate the adjusted frequency.

Abstract: A power-on method for a computer system comprising a processor supporting Hyper-Threading, a Read Only Memory (ROM) and a main memory, wherein the processor comprises a cache memory and the ROM comprises BIOS codes. The power-on method comprises the following steps. First, the processor is initialized in a Hyper-Threading disabled mode. The BIOS codes is then copied from the ROM to the cache memory, and the main memory is initialized by executing the BIOS codes therein. Thereafter, the processor is re-initialized in a Hyper-Threading enabled mode after the main memory is initialized. The processor comprises a first logic unit and a second logic unit. When initializing the processor, a first potential is applied to pin A31 of the processor, and a reset signal is delivered to the processor while the pin A31 is at the first potential, such that the processor is initialized in the Hyper-Threading disabled mode.

Abstract: A device for burst reading/writing memory data includes a memory module and a north bridge chipset. The device is used for executing a power on self test (POST). The memory module has a plurality of memory cells and the north bridge chipset includes a programmable register module and a memory module controller, wherein the programmable register module stores at least one set of default information. The memory module controller performing burst read/write on the memory cells according to the default information stored in the programmable register module.

Abstract: A memory initialization method for a plurality of memories. The memories are initialized according to predetermined initial parameters. A first quantity of the memories is detected. Optimum parameters are set according hardware information of the memories. The memories are re-initialized according to the optimum parameters. A second quantity of the memories is detected. The parameters for memory initialization are adjusted when the first quantity and the second quantity are different.

Abstract: A computer reset method activated by a South Bridge to directly reset a Central Processing Unit (CPU). First, a trigger signal is received. A CPU reset signal is delivered by the South Bridge when receiving the trigger signal. Thereafter, the CPU is reset when receiving the CPU reset signal from the South Bridge via a North Bridge.

Abstract: A motherboard includes a south-bridge chipset, a north-bridge chipset and a central processor unit (CPU). The south-bridge chipset generates at least control-setting data. The north-bridge chipset has a reset register for controlling the north-bridge chipset to generate a reset signal and a control-set resister for storing the control-setting data generated by the south-bridge chipset. The CPU has a plurality of configuration parameters. The configuration parameters of the CPU are reset in accordance with the reset signal, and the control-setting data is written into the CPU by the north-bridge chipset to set one of the configuration parameters of the CPU.

Abstract: A device for DRAM initialization of a computer system. A detection circuit detects memory condition and outputs a fast initialization signal. A buffer stores initialization parameters of the memory. A memory controller sets the initialization parameters according to memory information, and reads the memory condition to initialize the memory when booting and receiving the fast initialization signal.

Abstract: A data processing method of a virtual optical disk applied in an optical disk system is provided. The method includes steps as follows: Firstly a sound source determining procedure is executed. If the sound source is not from a virtual optical disk, a pre-processing and a buffer playing process are executed, and also a state changing process is executed while the buffer playing process is executed. According to a result of the state changing process, one of the following three steps is executed: the sound source determining procedure, the pre-processing procedure, and an idle determining procedure. If the system is not idling when executing the idle determining procedure, the buffer playing process is thus executed. Otherwise, a state assessment process is then executed. In accordance with the state assessment process, a storage capacity planning procedure, a write process or the state changing process is then executed.

Abstract: A frequency working between the north bridge chip and random access memory of a computer system is dynamically and automatically adjusted in response to the frequency change of the CPU, in response to the workload of the north bridge chip or in response to the change of settings in a software program. The computer system may need to perform POST (Power-On Self Test) of BIOS to detect and calibrate the adjusted frequency.

Abstract: The present invention relates to a memory-refreshing method applied to a computer system. The computer system includes a central processing unit (CPU), a north bridge chip in communication with the CPU and a system memory in communication with the north bridge chip. The system memory includes at least a first storage zone and a second storage zone. The first storage zone stores a specific data that remains refreshed when the CPU is in a first power-saving mode.

Abstract: A power-on method for a computer system comprising a processor supporting Hyper-Threading, a Read Only Memory (ROM) and a main memory, wherein the processor comprises a cache memory and the ROM comprises BIOS codes. The power-on method comprises the following steps. First, the processor is initialized in a Hyper-Threading disabled mode. The BIOS codes is then copied from the ROM to the cache memory, and the main memory is initialized by executing the BIOS codes therein. Thereafter, the processor is re-initialized in a Hyper-Threading enabled mode after the main memory is initialized. The processor comprises a first logic unit and a second logic unit. When initializing the processor, a first potential is applied to pin A31 of the processor, and a reset signal is delivered to the processor while the pin A31 is at the first potential, such that the processor is initialized in the Hyper-Threading disabled mode.

Abstract: A computer reset method activated by a South Bridge to directly reset a Central Processing Unit (CPU). First, a trigger signal is received. A CPU reset signal is delivered by the South Bridge when receiving the trigger signal. Thereafter, the CPU is reset when receiving the CPU reset signal from the South Bridge via a North Bridge.

Abstract: A memory initialization method for a plurality of memories. The memories are initialized according to predetermined initial parameters. A first quantity of the memories is detected. Optimum parameters are set according hardware information of the memories. The memories are re-initialized according to the optimum parameters. A second quantity of the memories is detected. The parameters for memory initialization are adjusted when the first quantity and the second quantity are different.

Abstract: Disclosed is a video and audio playing device. When play data of each disk in a disk selection unit is not stored in a non-volatile memory unit, a control unit controls a reading unit to read the play data of each disk, so as to store to a non-volatile memory unit. When a user chooses the disk to play by selecting from a navigating key, the control unit collects the play data of the disk stored in the non-volatile memory unit, and also stores to a volatile memory unit. Afterwards, when media contents of the disks are played, the control unit collects the play data stored in the volatile memory unit, and then displays the play data on a display unit.

Abstract: A data processing method of a virtual optical disk applied in an optical disk system is provided. The method includes steps as follows: Firstly a sound source determining procedure is executed. If the sound source is not from a virtual optical disk, a pre-processing and a buffer playing process are executed, and also a state changing process is executed while the buffer playing process is executed. According to a result of the state changing process, one of the following three steps is executed: the sound source determining procedure, the pre-processing procedure, and an idle determining procedure. If the system is not idling when executing the idle determining procedure, the buffer playing process is thus executed. Otherwise, a state assessment process is then executed. In accordance with the state assessment process, a storage capacity planning procedure, a write process or the state changing process is then executed.