Patents by Inventor Hsiu-Ming WU

Hsiu-Ming WU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250006831
    Abstract: A semiconductor device and a method for forming the same are provided. The semiconductor device includes a substrate, a buffer layer on the substrate, a channel layer on the buffer layer, a barrier layer on the channel layer and a gate structure on the barrier layer. The gate structure includes a gate layer, a gate electrode layer, a first protection pattern layer and second protection spacers. The gate electrode layer covers the gate layer. The first protection pattern layer covers a first top surface of the gate electrode layer. The second protection spacers cover first side surfaces of the gate electrode layer, second side surfaces of the first protection pattern layer and a portion of the gate layer. First interfaces between the second protection spacers and the gate layer are coplanar with a second interface, which is between the gate electrode layer and the gate layer.
    Type: Application
    Filed: June 28, 2023
    Publication date: January 2, 2025
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Cheng-Wei CHOU, Yung-Fong LIN, Shin-Cheng LIN, Hsiu-Ming WU
  • Patent number: 11450764
    Abstract: A method of forming a semiconductor device includes: providing a substrate, wherein a buffer layer, a channel layer, and a barrier layer are sequentially formed on the substrate; forming a doped compound semiconductor layer on a portion of the barrier layer; forming a first etch stop layer on the doped compound semiconductor layer; forming a second etch stop layer on the first etch stop layer; forming a first dielectric layer on the second etch stop layer; forming an etch protection layer on the first dielectric layer; performing a first etch process to form a recess in the first dielectric layer; performing a second etch process to form an opening exposing a portion of the second etch stop layer; performing a removal process to remove remaining portions of the etch protection layer on the first dielectric layer; and forming a gate metal layer to fill the opening.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: September 20, 2022
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Cheng-Wei Chou, Hsiu-Ming Wu
  • Publication number: 20220208992
    Abstract: A method of forming a semiconductor device includes: providing a substrate, wherein a buffer layer, a channel layer, and a barrier layer are sequentially formed on the substrate; forming a doped compound semiconductor layer on a portion of the barrier layer; forming a first etch stop layer on the doped compound semiconductor layer; forming a second etch stop layer on the first etch stop layer; forming a first dielectric layer on the second etch stop layer; forming an etch protection layer on the first dielectric layer; performing a first etch process to form a recess in the first dielectric layer; performing a second etch process to form an opening exposing a portion of the second etch stop layer; performing a removal process to remove remaining portions of the etch protection layer on the first dielectric layer; and forming a gate metal layer to fill the opening.
    Type: Application
    Filed: December 29, 2020
    Publication date: June 30, 2022
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Cheng-Wei CHOU, Hsiu-Ming WU