Patents by Inventor Hsiu-Ping Wei

Hsiu-Ping Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240030158
    Abstract: Systems and methods are provided for reducing damage caused by defects from a scribe lane of an integrated circuit, which may arise during or after a silicon wafer is singulated into separate integrated circuits. An integrated circuit may include an active area and a scribe lane. The scribe lane may include a crack energy release zone or a crack take-off zone, or both. The crack energy release zone may dissipate fracture energy in an event that a crack were to form in the scribe lane. The crack take-off zone may, in the event that the crack were to form in the scribe lane, guide the crack out of a surface of the integrated circuit in the crack take-off zone.
    Type: Application
    Filed: July 20, 2023
    Publication date: January 25, 2024
    Inventors: Szu-Ying Ho, Jeng-Wen P Chen, Hsiu-Ping Wei
  • Patent number: 9536847
    Abstract: An embodiment is a bump bond pad structure that comprises a substrate comprising a top layer, a reinforcement pad disposed on the top layer, an intermediate layer above the top layer, an intermediate connection pad disposed on the intermediate layer, an outer layer above the intermediate layer, and an under bump metal (UBM) connected to the intermediate connection pad through an opening in the outer layer. Further embodiments may comprise a via mechanically coupling the intermediate connection pad to the reinforcement pad. The via may comprise a feature selected from the group consisting of a solid via, a substantially ring-shaped via, or a five by five array of vias. Yet, a further embodiment may comprise a secondary reinforcement pad, and a second via mechanically coupling the reinforcement pad to the secondary reinforcement pad.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: January 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiu-Ping Wei, Hsien-Wei Chen, Hao-Yi Tsai, Ying-Ju Chen, Yu-Wen Liu
  • Publication number: 20160035684
    Abstract: An embodiment is a bump bond pad structure that comprises a substrate comprising a top layer, a reinforcement pad disposed on the top layer, an intermediate layer above the top layer, an intermediate connection pad disposed on the intermediate layer, an outer layer above the intermediate layer, and an under bump metal (UBM) connected to the intermediate connection pad through an opening in the outer layer. Further embodiments may comprise a via mechanically coupling the intermediate connection pad to the reinforcement pad. The via may comprise a feature selected from the group consisting of a solid via, a substantially ring-shaped via, or a five by five array of vias. Yet, a further embodiment may comprise a secondary reinforcement pad, and a second via mechanically coupling the reinforcement pad to the secondary reinforcement pad.
    Type: Application
    Filed: October 15, 2015
    Publication date: February 4, 2016
    Inventors: Hsiu-Ping Wei, Hsien-Wei Chen, Hao-Yi Tsai, Ying-Ju Chen, Yu-Wen Liu
  • Patent number: 9171811
    Abstract: An embodiment is a bump bond pad structure that comprises a substrate comprising a top layer, a reinforcement pad disposed on the top layer, an intermediate layer above the top layer, an intermediate connection pad disposed on the intermediate layer, an outer layer above the intermediate layer, and an under bump metal (UBM) connected to the intermediate connection pad through an opening in the outer layer. Further embodiments may comprise a via mechanically coupling the intermediate connection pad to the reinforcement pad. The via may comprise a feature selected from the group consisting of a solid via, a substantially ring-shaped via, or a five by five array of vias. Yet, a further embodiment may comprise a secondary reinforcement pad, and a second via mechanically coupling the reinforcement pad to the secondary reinforcement pad.
    Type: Grant
    Filed: October 13, 2014
    Date of Patent: October 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Hsien-Wei Chen, Yu-Wen Liu, Ying-Ju Chen, Hsiu-Ping Wei
  • Publication number: 20150031200
    Abstract: An embodiment is a bump bond pad structure that comprises a substrate comprising a top layer, a reinforcement pad disposed on the top layer, an intermediate layer above the top layer, an intermediate connection pad disposed on the intermediate layer, an outer layer above the intermediate layer, and an under bump metal (UBM) connected to the intermediate connection pad through an opening in the outer layer. Further embodiments may comprise a via mechanically coupling the intermediate connection pad to the reinforcement pad. The via may comprise a feature selected from the group consisting of a solid via, a substantially ring-shaped via, or a five by five array of vias. Yet, a further embodiment may comprise a secondary reinforcement pad, and a second via mechanically coupling the reinforcement pad to the secondary reinforcement pad.
    Type: Application
    Filed: October 13, 2014
    Publication date: January 29, 2015
    Inventors: Hao-Yi Tsai, Hsien-Wei Chen, Yu-Wen Liu, Ying-Ju Chen, Hsiu-Ping Wei
  • Patent number: 8907478
    Abstract: An embodiment is a bump bond pad structure that comprises a substrate comprising a top layer, a reinforcement pad disposed on the top layer, an intermediate layer above the top layer, an intermediate connection pad disposed on the intermediate layer, an outer layer above the intermediate layer, and an under bump metal (UBM) connected to the intermediate connection pad through an opening in the outer layer. Further embodiments may comprise a via mechanically coupling the intermediate connection pad to the reinforcement pad. The via may comprise a feature selected from the group consisting of a solid via, a substantially ring-shaped via, or a five by five array of vias. Yet, a further embodiment may comprise a secondary reinforcement pad, and a second via mechanically coupling the reinforcement pad to the secondary reinforcement pad.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: December 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Hsien-Wei Chen, Yu-Wen Liu, Ying-Ju Chen, Hsiu-Ping Wei
  • Patent number: 8753971
    Abstract: A method of forming an integrated circuit structure is provided. The method includes forming a metal pad at a major surface of a semiconductor chip, forming an under-bump metallurgy (UBM) over the metal pad such that the UBM and the metal pad are in contact, forming a dummy pattern at a same level as the metal pad, the dummy pattern formed of a same metallic material as the metal pad and electrically disconnected from the metal pad, and forming a metal bump over the UBM such that the metal bump is electrically connected to the UBM and no metal bump in the semiconductor chip is formed over the dummy pattern.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: June 17, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzuan-Horng Liu, Shang-Yun Hou, Shin-Puu Jeng, Wei-Cheng Wu, Hsiu-Ping Wei, Chih-Hua Chen, Chen-Cheng Kuo, Chen-Shien Chen, Ming Hung Tseng
  • Patent number: 8405211
    Abstract: An embodiment is a bump bond pad structure that comprises a substrate comprising a top layer, a reinforcement pad disposed on the top layer, an intermediate layer above the top layer, an intermediate connection pad disposed on the intermediate layer, an outer layer above the intermediate layer, and an under bump metal (UBM) connected to the intermediate connection pad through an opening in the outer layer. Further embodiments may comprise a via mechanically coupling the intermediate connection pad to the reinforcement pad. The via may comprise a feature selected from the group consisting of a solid via, a substantially ring-shaped via, or a five by five array of vias. Yet, a further embodiment may comprise a secondary reinforcement pad, and a second via mechanically coupling the reinforcement pad to the secondary reinforcement pad.
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: March 26, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Hsien-Wei Chen, Yu-Wen Liu, Ying-Ju Chen, Hsiu-Ping Wei
  • Patent number: 8227916
    Abstract: A semiconductor package structure is provided. The structure includes a semiconductor chip having a plurality of interconnect layers formed thereover. A first passivation layer is formed over the plurality of interconnect layers. A stress buffer layer is formed over the first passivation layer. A bonding pad is formed over the stress buffer layer. A second passivation layer is formed over a portion of the bonding pad, the second passivation having at least one opening therein exposing a portion of the bonding pad.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: July 24, 2012
    Inventors: Hsiu-Ping Wei, Shin-Puu Jeng, Hao-Yi Tsai, Hsien-Wei Chen, Yu-Wen Liu, Ying-Ju Chen, Tzuan-Horng Liu
  • Publication number: 20120178252
    Abstract: A method of forming an integrated circuit structure is provided. The method includes forming a metal pad at a major surface of a semiconductor chip, forming an under-bump metallurgy (UBM) over the metal pad such that the UBM and the metal pad are in contact, forming a dummy pattern at a same level as the metal pad, the dummy pattern formed of a same metallic material as the metal pad and electrically disconnected from the metal pad, and forming a metal bump over the UBM such that the metal bump is electrically connected to the UBM and no metal bump in the semiconductor chip is formed over the dummy pattern.
    Type: Application
    Filed: March 22, 2012
    Publication date: July 12, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzuan-Horng Liu, Shang-Yun Hou, Shin-Puu Jeng, Wei-Cheng Wu, Hsiu-Ping Wei, Chih-Hua Chen, Chen-Cheng Kuo, Chen-Shien Chen, Ming Hung Tseng
  • Patent number: 8193639
    Abstract: An integrated circuit structure includes a semiconductor chip, a metal pad at a major surface of the semiconductor chip, and an under-bump metallurgy (UBM) over and contacting the metal pad. A metal bump is formed over and electrically connected to the UBM. A dummy pattern is formed at a same level, and formed of a same metallic material, as the metal pad.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: June 5, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzuan-Horng Liu, Shang-Yun Hou, Shin-Puu Jeng, Wei-Cheng Wu, Hsiu-Ping Wei, Chih-Hua Chen, Chen-Cheng Kuo, Chen-Shien Chen, Ming Hung Tseng
  • Publication number: 20110241202
    Abstract: An integrated circuit structure includes a semiconductor chip, a metal pad at a major surface of the semiconductor chip, and an under-bump metallurgy (UBM) over and contacting the metal pad. A metal bump is formed over and electrically connected to the UBM. A dummy pattern is formed at a same level, and formed of a same metallic material, as the metal pad.
    Type: Application
    Filed: March 30, 2010
    Publication date: October 6, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzuan-Horng Liu, Shang-Yun Hou, Shin-Puu Jeng, Wei-Cheng Wu, Hsiu-Ping Wei, Chih-Hua Chen, Chen-Cheng Kuo, Chen-Shien Chen, Ming Hung Tseng
  • Patent number: 8030776
    Abstract: A structure includes a semiconductor substrate having semiconductor devices formed on or in the substrate. An interconnecting metallization structure is formed over and connected to the devices. The interconnecting metallization structure including at least one dielectric layer. A passivation layer is deposited over the interconnecting metallization structure and the dielectric layer. At least one metal contact pad and at least one dummy metal structure are provided in the passivation layer. The contact pad is conductively coupled to at least one of the devices. The dummy metal structure is spaced apart from the contact pad and unconnected to the contact pad and the devices.
    Type: Grant
    Filed: October 7, 2009
    Date of Patent: October 4, 2011
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Shin-Puu Jeng, Shang-Yun Hou, Hao-Yi Tsai, Hsien Wei Chen, Hsiu-Ping Wei
  • Publication number: 20110079922
    Abstract: A structure includes a semiconductor substrate having semiconductor devices formed on or in the substrate. An interconnecting metallization structure is formed over and connected to the devices. The interconnecting metallization structure including at least one dielectric layer. A passivation layer is deposited over the interconnecting metallization structure and the dielectric layer. At least one metal contact pad and at least one dummy metal structure are provided in the passivation layer. The contact pad is conductively coupled to at least one of the devices. The dummy metal structure is spaced apart from the contact pad and unconnected to the contact pad and the devices.
    Type: Application
    Filed: October 7, 2009
    Publication date: April 7, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Hua Yu, Shin-Puu Jeng, Shang-Yun Hou, Hao-Yi Tsai, Hsien Wei Chen, Hsiu-Ping WEI
  • Publication number: 20110018128
    Abstract: A semiconductor package structure is provided. The structure includes a semiconductor chip having a plurality of interconnect layers formed thereover. A first passivation layer is formed over the plurality of interconnect layers. A stress buffer layer is formed over the first passivation layer. A bonding pad is formed over the stress buffer layer. A second passivation layer is formed over a portion of the bonding pad, the second passivation having at least one opening therein exposing a portion of the bonding pad.
    Type: Application
    Filed: April 9, 2010
    Publication date: January 27, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiu-Ping WEI, Shin-Puu JENG, Hao-Yi TSAI, Hsien-Wei CHEN, Yu-Wen LIU, Ying-Ju CHEN, Tzuan-Horng LIU
  • Publication number: 20100283148
    Abstract: An embodiment is a bump bond pad structure that comprises a substrate comprising a top layer, a reinforcement pad disposed on the top layer, an intermediate layer above the top layer, an intermediate connection pad disposed on the intermediate layer, an outer layer above the intermediate layer, and an under bump metal (UBM) connected to the intermediate connection pad through an opening in the outer layer. Further embodiments may comprise a via mechanically coupling the intermediate connection pad to the reinforcement pad. The via may comprise a feature selected from the group consisting of a solid via, a substantially ring-shaped via, or a five by five array of vias. Yet, a further embodiment may comprise a secondary reinforcement pad, and a second via mechanically coupling the reinforcement pad to the secondary reinforcement pad.
    Type: Application
    Filed: March 18, 2010
    Publication date: November 11, 2010
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Hsien-Wei Chen, Yu-Wen Liu, Ying-Ju Chen, Hsiu-Ping Wei