Patents by Inventor Hsiu-Wen WU

Hsiu-Wen WU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11901228
    Abstract: In an embodiment, a method includes forming a first conductive feature in a first inter-metal dielectric (IMD) layer; depositing a blocking film over and physically contacting the first conductive feature; depositing a first dielectric layer over and physically contacting the first IMD layer; depositing a second dielectric layer over and physically contacting the first dielectric layer; removing the blocking film; depositing an etch stop layer over any physically contacting the first conductive feature and the second dielectric layer; forming a second IMD layer over the etch stop layer; etching an opening in the second IMD layer and the etch stop layer to expose the first conductive feature; and forming a second conductive feature in the opening.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cai-Ling Wu, Hsiu-Wen Hsueh, Wei-Ren Wang, Po-Hsiang Huang, Chii-Ping Chen, Jen Hung Wang
  • Publication number: 20230411210
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises an interlayer dielectric (ILD) layer disposed over a substrate; a first conductive feature at least partially embedded in the ILD layer; a dielectric layer disposed over and aligned with the ILD layer, wherein a top surface of the dielectric layer is above a top surface of the first conductive feature; an etch stop layer (ESL) disposed over the dielectric layer and over the first conductive feature; and a second conductive feature disposed on the first conductive feature, wherein the second conductive feature includes a first portion having a first bottom surface contacting a top surface of the first conductive feature and a second portion having a second bottom surface contacting a top surface of the dielectric layer.
    Type: Application
    Filed: August 10, 2023
    Publication date: December 21, 2023
    Inventors: Hsiu-Wen Hsueh, Cai-Ling Wu, Ya-Ching Tseng, Chii-Ping Chen, Neng-Jye Yang
  • Patent number: 11830770
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises an interlayer dielectric (ILD) layer disposed over a substrate; a first conductive feature at least partially embedded in the ILD layer; a dielectric layer disposed over and aligned with the ILD layer, wherein a top surface of the dielectric layer is above a top surface of the first conductive feature; an etch stop layer (ESL) disposed over the dielectric layer and over the first conductive feature; and a second conductive feature disposed on the first conductive feature, wherein the second conductive feature includes a first portion having a first bottom surface contacting a top surface of the first conductive feature and a second portion having a second bottom surface contacting a top surface of the dielectric layer.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: November 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Hsiu-Wen Hsueh, Cai-Ling Wu, Ya-Ching Tseng, Chii-Ping Chen, Neng-Jye Yang
  • Publication number: 20230377966
    Abstract: In an embodiment, a method includes forming a first conductive feature in a first inter-metal dielectric (IMD) layer; depositing a blocking film over and physically contacting the first conductive feature; depositing a first dielectric layer over and physically contacting the first IMD layer; depositing a second dielectric layer over and physically contacting the first dielectric layer; removing the blocking film; depositing an etch stop layer over any physically contacting the first conductive feature and the second dielectric layer; forming a second IMD layer over the etch stop layer; etching an opening in the second IMD layer and the etch stop layer to expose the first conductive feature; and forming a second conductive feature in the opening.
    Type: Application
    Filed: August 4, 2023
    Publication date: November 23, 2023
    Inventors: Cai-Ling Wu, Hsiu-Wen Hsueh, Wei-Ren Wang, Po-Hsiang Huang, Chii-Ping Chen, Jen Hung Wang
  • Publication number: 20230378169
    Abstract: The present disclosure provides a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device comprises a substrate, a first gate electrode, a second gate electrode, a first doped region, a second doped region, a third doped region, and a first interconnection structure. The substrate comprises a well region of a first conductive type. The first and second gate electrodes are disposed on the substrate. The first, second, and third doped regions are embedded within the well region and are of the first conductive type. The first interconnection structure electrically connects the first gate electrode and the second gate electrode. The first doped region and the second doped region are disposed on opposite sides of the first gate electrode.
    Type: Application
    Filed: May 18, 2022
    Publication date: November 23, 2023
    Inventors: HO-HSIANG CHEN, CHI-HSIEN LIN, YING-TA LU, HSIEN-YUAN LIAO, HSIU-WEN WU, CHIAO-HAN LEE, TZU-JIN YEH
  • Publication number: 20230369226
    Abstract: A method for forming a semiconductor device structure is provided. The method includes removing a portion of a dielectric layer to form a trench in the dielectric layer. The method includes forming a barrier layer in the trench. The method includes forming a seed layer in the trench and over the barrier layer. The seed layer is doped with manganese. The method includes annealing the seed layer in a first process gas including a first hydrogen gas. A volume ratio of the first hydrogen gas to the first process gas ranges from about 50% to about 100%, and the manganese diffuses from the seed layer to the barrier layer during the annealing of the seed layer in the first process gas.
    Type: Application
    Filed: May 11, 2022
    Publication date: November 16, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cai-Ling WU, Hsiu-Wen HSUEH, Chii-Ping CHEN, Po-Hsiang HUANG, Chi-Feng LIN
  • Publication number: 20230282644
    Abstract: A cell layout design for an integrated circuit. In one embodiment, the integrated circuit includes a dual-gate cell forming two transistors connected with each other via a common source/drain terminal. The dual-gate cell includes an active region, two gate lines extending across the active region, at least one first gate via disposed on one or both of the two gate lines and overlapped with the active region, and second gate vias disposed on one or both of the two gate lines and located outside the active region.
    Type: Application
    Filed: June 30, 2022
    Publication date: September 7, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ho-Hsiang CHEN, Chi-Hsien LIN, Ying-Ta LU, Hsien-Yuan LIAO, Hsiu-Wen WU, Chiao-Han LEE, Tzu-Jin YEH