Abstract: A multilayer polymer capacitor (MLPC), including a casing, a multilayer core, an electroplated positive terminal, a first electroplated negative terminal, and a second electroplated negative terminal. The casing includes a casing body and a cover plate. The casing body is provided with an accommodating cavity, whose bottom is provided with a through hole. The multilayer core is provided in the accommodating cavity. An anode lead-out part and a cathode lead-out part are provided at two ends of the accommodating cavity, respectively. The electroplated positive terminal and the first electroplated negative terminal are provided on outer side surfaces of two ends of the casing, respectively. The second electroplated negative terminal is provided on an outer bottom surface of the casing, and is electrically connected to the multilayer core.

Abstract: A semiconductor device includes a substrate including a well region of a first conductive type; a first gate electrode on the substrate; a second gate electrode on the substrate; a first doped region embedded within the well region and is of the first conductive type, a second doped region embedded within the well region and is of the first conductive type, and a third doped region embedded within the well region and is of the first conductive type; and a first interconnection structure electrically connecting the first gate electrode and the second gate electrode. The first doped region and the second doped region are on opposite sides of the first gate electrode.

Abstract: The present disclosure provides a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device comprises a substrate, a first gate electrode, a second gate electrode, a first doped region, a second doped region, a third doped region, and a first interconnection structure. The substrate comprises a well region of a first conductive type. The first and second gate electrodes are disposed on the substrate. The first, second, and third doped regions are embedded within the well region and are of the first conductive type. The first interconnection structure electrically connects the first gate electrode and the second gate electrode. The first doped region and the second doped region are disposed on opposite sides of the first gate electrode.

Abstract: A cell layout design for an integrated circuit. In one embodiment, the integrated circuit includes a dual-gate cell forming two transistors connected with each other via a common source/drain terminal. The dual-gate cell includes an active region, two gate lines extending across the active region, at least one first gate via disposed on one or both of the two gate lines and overlapped with the active region, and second gate vias disposed on one or both of the two gate lines and located outside the active region.