Abstract: The present disclosure involves a semiconductor device. The semiconductor device includes a substrate. The semiconductor device includes an electronic device positioned over the substrate. The electronic device includes an opening. The semiconductor device includes a shielding device positioned over the substrate and surrounding the electronic device. The shielding device includes a plurality of elongate members. A subset of the plurality of elongate members extend through the opening of the electronic device. At least one of the electronic device and the shielding device is formed in an interconnect structure positioned over the substrate.

Abstract: The present disclosure involves a semiconductor device. The semiconductor device includes a substrate. The semiconductor device includes an electronic device positioned over the substrate. The electronic device includes an opening. The semiconductor device includes a shielding device positioned over the substrate and surrounding the electronic device. The shielding device includes a plurality of elongate members. A subset of the plurality of elongate members extend through the opening of the electronic device. At least one of the electronic device and the shielding device is formed in an interconnect structure positioned over the substrate.

Abstract: A planar interdigitated capacitor structure, methods of forming, and devices including, the same. The device includes first and second planar electrode structures including respective first and second pluralities of planar continuous rectangular plate electrode elements formed above a semiconductor substrate and extending continuously in first and second orthogonal directions substantially parallel to a plane of the substrate, and first and second conductors interconnecting the respective first and second pluralities of planar electrode elements parallel to a third axis substantially normal to the plane of the substrate. The first and second planar electrode structures are arranged with respective continuous rectangular plate electrode elements of each planar electrode structure interleaved and substantially parallel with each other between the first and second conductors. The device also includes a dielectric material between the first planar electrode structure and the second planar electrode structure.

Abstract: A short dummy test structure is disclosed, including a grounded shield layer above a substrate, at least two signal test pads, and a signal transmission line above the grounded shield layer and between the two signal test pads, wherein the signal transmission line is electrically coupled to the grounded shield layer. In one embodiment, the signal transmission line has a smaller total length than a total length of a corresponding signal transmission line and a device-under-test (DUT) of a test structure including the DUT. A de-embedding apparatus and method of de-embedding utilizing such a short dummy test structure are also disclosed.

Abstract: A planar interdigitated capacitor structure, methods of forming, and devices including, the same. The device includes first and second planar electrode structures including respective first and second pluralities of planar continuous rectangular plate electrode elements formed above a semiconductor substrate and extending continuously in first and second orthogonal directions substantially parallel to a plane of the substrate, and first and second conductors interconnecting the respective first and second pluralities of planar electrode elements parallel to a third axis substantially normal to the plane of the substrate. The first and second planar electrode structures are arranged with respective continuous rectangular plate electrode elements of each planar electrode structure interleaved and substantially parallel with each other between the first and second conductors. The device also includes a dielectric material between the first planar electrode structure and the second planar electrode structure.

Abstract: The present disclosure relates to a semiconductor device, such as a transistor. The device includes a gate terminal, a source terminal, a drain terminal, a transconductance component, and a boost component. The gate terminal is configured to receive a bias voltage. The drain terminal is coupled to the boost component. The transconductance component is coupled to the gate terminal, the source terminal and the drain terminal and provides an output current proportional to the bias voltage. The boost component is coupled to the transconductance component and boosts the output current at a selected frequency range.

Abstract: An embodiment is a method for de-embedding. The method comprises forming a primary structure in a semiconductor chip and forming an auxiliary structure in the semiconductor chip. The auxiliary structure replicates a first portion of the primary structure. The method further comprises determining a transmission matrix for each of the primary structure and the auxiliary structure based on measurements and extracting a transmission matrix of a first component of the primary structure by determining a product of the transmission matrix of the primary structure and an inverse of the transmission matrix of the auxiliary structure.

Abstract: The present disclosure involves a semiconductor device. The semiconductor device includes a substrate; a capacitor disposed over the substrate; an inductor disposed over the substrate and having a coil feature surrounding the capacitor; and a shielding structure over the substrate and configured around the coil feature.

Abstract: De-embedding apparatus and methods of de-embedding are disclosed. A de-embedding apparatus includes a test structure including a device-under-test (DUT) embedded in the test structure, and a plurality of dummy test structures including an open dummy structure, a distributed open dummy structure, and a short dummy structure.

Abstract: An integrated circuit includes a substrate having a surface. An inductor is disposed over the surface of the substrate. The inductor is operable to generate a magnetic field through itself that is substantially parallel with the surface.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a surface that is defined by a first axis and a second axis perpendicular to the first axis; and a capacitor disposed on the substrate, the capacitor having an anode component that includes a plurality of first conductive features and a cathode component that includes a plurality of second conductive features. The first conductive features and the second conductive features each include two metal lines extending along the first axis. At least one metal via extending along a third axis that is perpendicular to the surface of the substrate and interconnecting the two metal lines. The first conductive features are interdigitated with the second conductive features along both the second axis and the third axis.

Abstract: A vertical inductor structure in a semiconductor device includes a plurality of vertically oriented spirals that produce magnetic field in a dielectric material above the surface of a semiconductor substrate thereby preventing any eddy currents from propagating in the substrate. An inductor shield structure is also provided. The inductor shield structure is formed over the substrate surface and between an inductor such as the vertical inductor structure or other inductor types and also prevents eddy currents from being induced in the substrate. The inductor shield may surround the inductor to various degrees.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate that spans in an X-direction and a Y-direction that is orthogonal to the X-direction. The semiconductor device includes an interconnect structure formed over the substrate in a Z-direction that is orthogonal to both the X-direction and the Y-direction. The interconnect structure includes a plurality of metal lines interconnected together in the Z-direction by a plurality of vias. The interconnect structure contains a transformer device that includes a primary coil and a secondary coil. The primary coil and the secondary coil are each wound at least partially in the Z-direction.

Abstract: The present disclosure involves a semiconductor device. The semiconductor device includes a substrate. The semiconductor device includes an electronic device positioned over the substrate. The electronic device includes an opening. The semiconductor device includes a shielding device positioned over the substrate and surrounding the electronic device. The shielding device includes a plurality of elongate members. A subset of the plurality of elongate members extend through the opening of the electronic device. At least one of the electronic device and the shielding device is formed in an interconnect structure positioned over the substrate.

Abstract: The present disclosure involves a semiconductor device. The semiconductor device includes a substrate having a horizontal surface. The semiconductor device includes an interconnect structure formed over the horizontal surface of the substrate. The interconnect structure includes an inductor coil that is wound substantially in a vertical plane that is orthogonal to the horizontal surface of the substrate. The interconnect structure includes a capacitor disposed proximate to the inductor coil. The capacitor has an anode component and a cathode component. The inductor coil and the capacitor each include a plurality of horizontally extending elongate members.

Abstract: A method includes simulating characteristics of a first transmission line having a first length, and simulating characteristics of a second transmission line having a second length greater than the first length. A calculation is then performed on the characteristics of the first transmission line and the characteristics of the second transmission line to generate intrinsic characteristics of a third transmission line having a length equal to a difference of the second length and the first length.

Abstract: An integrated circuit structure includes a semiconductor substrate; an interconnect structure over the semiconductor substrate; a first dielectric layer over the semiconductor substrate and in the interconnect structure; a second dielectric layer in the interconnect structure and over the first dielectric layer; and a wave-guide. The wave-guide includes a first portion in the first dielectric layer and a second portion in the second dielectric layer. The first portion adjoins the second portion.

Abstract: An integrated circuit includes a substrate having a surface. An inductor is disposed over the surface of the substrate. The inductor is operable to generate a magnetic field through itself that is substantially parallel with the surface.

Abstract: An integrated circuit structure includes a semiconductor substrate; an interconnect structure over the semiconductor substrate; a first dielectric layer over the semiconductor substrate and in the interconnect structure; a second dielectric layer in the interconnect structure and over the first dielectric layer; and a wave-guide. The wave-guide includes a first portion in the first dielectric layer and a second portion in the second dielectric layer. The first portion adjoins the second portion.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate that spans in an X-direction and a Y-direction that is orthogonal to the X-direction. The semiconductor device includes an interconnect structure formed over the substrate in a Z-direction that is orthogonal to both the X-direction and the Y-direction. The interconnect structure includes a plurality of metal lines interconnected together in the Z-direction by a plurality of vias. The interconnect structure contains a capacitor that includes an anode component and a cathode component. The anode component includes an array of elongate anode stack elements extending in the Z-direction. The cathode component includes an array of elongate cathode stack elements extending in the Z-direction. The array of anode stack elements are interdigitated with the array of cathode stack elements in both the X direction and the Y direction.