Abstract: Disclosed are a test piece and the manufacturing method thereof The test piece includes an insulating substrate and a circuit pattern structure formed on the insulating substrate, wherein circuit pattern structure includes a first metal pattern layer, a second metal pattern layer, a third metal pattern layer, a fourth metal pattern layer, and a fifth metal pattern layer. The first metal pattern layer, the second metal pattern layer, the third metal pattern layer, the fourth metal pattern layer, and the fifth metal pattern layer have same pattern shapes and positions thereof are overlapping in a plane. The first metal pattern layer and the second metal pattern layer are nano-metal films formed by vacuum coating, therefore, the test piece has excellent uniformity of film and low resistance to provide a stable test current to prevent the judging mistakes and to improve the test efficiency.

Abstract: Disclosed are a test piece and the manufacturing method thereof The test piece includes an insulating substrate and a circuit pattern structure formed on the insulating substrate, wherein circuit pattern structure includes a first metal pattern layer, a second metal pattern layer, a third metal pattern layer, a fourth metal pattern layer, and a fifth metal pattern layer. The first metal pattern layer, the second metal pattern layer, the third metal pattern layer, the fourth metal pattern layer, and the fifth metal pattern layer have same pattern shapes and positions thereof are overlapping in a plane. The first metal pattern layer and the second metal pattern layer are nano-metal films formed by vacuum coating, therefore, the test piece has excellent uniformity of film and low resistance to provide a stable test current to prevent the judging mistakes and to improve the test efficiency.

Abstract: A structure and method for repairing SDRAM by generating a Slicing Table of Fault Distribution and using the size of SDRAM page as the partition basic block. The Slicing Table of Fault Distribution is generated at each booting or memory-testing, and the elemental range of the number of detected defects is formed. When the number of detected defects exceeds the elemental range, the limits of another partition block with a lower rate of defects are used to cure the defect. The repair bit is also encoded according to the Slicing Table of Fault Distribution, pointing to the remapping bit so that the access operation occurs at the remapping bit. As such, the cost of producing, testing and repairing SDRAM is greatly reduced.

Abstract: The present invention relates to a DRAM memory page operation method and its structure. The disclosed method comprises a set up procedure and an operation procedure. The set up procedure tests and finds out whether any deficit exists in the memory page of the memory and establishes a table of look-aside buffer that indicates defective locations and the corresponding new locations. The real operation procedure is executed after the set up procedure completes. It establishes a fast page lookup table according to results in the set up procedure for instructing the memory page or memory unit to operate in the normal access mode or the page operation mode. Good memory pages then replace bad memory pages according to the records in the fast page lookup table and the bad memory pages are moved to addresses at the very end of the memory so that the memory can operate even with deficits. Thus, no deficit in a single DRAM memory page/unit will halt the whole system.

Abstract: A framework and a respective method for inter-element channel transmission are introduced mainly by constructing a plurality of connecting channels between elements. Each channel further includes a plurality of signal lines. Implicit meaning (data, address or control signal) in the signal line is realized by judging the variation of duty cycle in a clock signal, or an A/C line is used to define the transmission of a start signature, an end signature, address signals and control signals. By providing the transmission models of the present invention, each channel can operate independently, perform unidirectional transmission of address and data signals, and adjust the channel arrangement in accordance with practical requirements. Thereby, the signal transmission between elements can be highly mobile, the idle transmission time between elements can be greatly reduced, and the optimal transmission efficiency can be achieved.

Abstract: This invention relates to a structure and method for repairing SDRAM by generating a Slicing Table of Fault Distribution and using the size of SDRAM page as the partition basic block. The Slicing Table of Fault Distribution is generated at each booting or memory-testing, and the elemental range of the number of detected defects is formed. When the number of detected defects exceeds the elemental range, the limits of the other partition block with lower rate of defect are used to cure the defect. The repair bit is also encoded according the Slicing Table of Fault Distribution, pointing to the remapping bit so that the access operation occurs at the remapping bit. As such, the cost of producing, testing and repairing SDRM is greatly reduced.

Abstract: A method of defects recovery and status display of dynamic random access memory(DRAM), which mainly start time test through a monitor program, and predetermine a spare memory page which serves as temporary storage of internal data while the memory page is tested, the internal data of the memory page which will be tested are duplicated to the predetermined memory page, and then a table of look-aside buffer(TLB) is built to map the location of the tested memory page to the predetermined spare memory page, the tested memory page is re-directed to the predetermined spare memory page through TLB, which makes normal access be re-directed to the spare memory page; while any memory page with defects is detected, the monitor program will continuously block the said tested memory page, and any access operation for the said memory page will re-direct to the predetermined spare memory page according to TLB, and LCD will be driven to display the message such as testing frequency, intact report, detected fault, sum of memo

Abstract: A structure of controlled pipeline logic is disclosed. A random noise generator is added to the controlled pipeline logic. Moreover, each combinational logic element of the controlled pipeline logic is appended with an active bit. When no input flows into the controlled pipeline logic, the random noise generator will generate random noises, and the active bit will enforce the combinational logic element to accept the random noise as an input so that the controlled pipeline logic is always sustained in the active condition. The controlled pipeline logic is not exposing the internal functions thereof and avoiding improper monitoring and observation.

Abstract: The present invention relates to a DRAM memory page operation method and its structure. The disclosed method comprises a set up procedure and an operation procedure. The set up procedure tests and finds out whether any deficit exists in the memory page of the memory and establishes a table of look-aside buffer that indicates defective locations and the corresponding new locations. The real operation procedure is executed after the set up procedure completes. It establishes a fast page lookup table according to results in the set up procedure for instructing the memory page or memory unit to operate in the normal access mode or the page operation mode. Good memory pages then replace bad memory pages according to the records in the fast page lookup table and the bad memory pages are moved to addresses at the very end of the memory so that the memory can operate even with deficits. Thus, no deficit in a single DRAM memory page/unit will halt the whole system.

Abstract: A data-processing system with an enhanced system controller supporting memory-remapping function. The system controller has an access control circuit, a page/remapping management circuit and an open/remapped address table. The open/remapped address table is used to store mapping tables for indicating the mapping relation of memory segments and addresses dedicated to peripheral devices. The page/remapping management circuit should maintain and use the mapping tables in various operating mode. In addition, the page/remapping management circuit can redirect access requests to proper memory segments according to the mapping table corresponding to the current operating mode. Therefore, peripheral devices can effectively access and process the data stored in various memory segments by the change of the operating modes, not by physical data transfer.