Patents by Inventor Hsu-Chen Cheng
Hsu-Chen Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240137709Abstract: An electro-acoustical transducer device is disclosed, which includes: a hollow disk body that generally defines an axis of propagation, the hollow disk body comprising: a pair of plate members extending substantially perpendicular to the axis of propagation, each provided with a central transmitting port arranged about the axis of propagation, and a peripheral enclosure jointing the pair of plate members at the respective outer edge portions thereof, thereby defining a chamber of resonance between the pair of plate members; wherein a ring-opening about the axis of propagation that enables access to the chamber of resonance is formed between the central transmitting ports of the plate members.Type: ApplicationFiled: April 27, 2023Publication date: April 25, 2024Inventors: YU-CHEN CHEN, CHUN-KAI CHAN, HSU-HSIANG CHENG, MING-CHING CHENG
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Publication number: 20210134298Abstract: A knowledge point mark generation system and a method thereof are provided. The system and the method thereof can obtain a label vocabulary by performing the analysis procedure on at least one second candidate vocabulary repeated by sound in a class, at least one first candidate vocabulary repeated by text during class, at least one second keyword highlighted by sound during class, and at least one first keyword highlighted by text during class according to their weights, and then set knowledge point marks on a timeline of a video file taken during class according to time periods when the label vocabulary appears. Thus, a learner can know the knowledge points of the class and their video clips in the video file without browsing the entire video file, so that it is convenient for the learner to learn or review the key points of the class.Type: ApplicationFiled: October 31, 2019Publication date: May 6, 2021Inventor: Hsu Chen CHENG
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Patent number: 10978077Abstract: A knowledge point mark generation system and a method thereof are provided. The system and the method thereof can obtain a label vocabulary by performing the analysis procedure on at least one second candidate vocabulary repeated by sound in a class, at least one first candidate vocabulary repeated by text during class, at least one second keyword highlighted by sound during class, and at least one first keyword highlighted by text during class according to their weights, and then set knowledge point marks on a timeline of a video file taken during class according to time periods when the label vocabulary appears. Thus, a learner can know the knowledge points of the class and their video clips in the video file without browsing the entire video file, so that it is convenient for the learner to learn or review the key points of the class.Type: GrantFiled: October 31, 2019Date of Patent: April 13, 2021Assignee: Wisdom Garden Hong Kong LimitedInventor: Hsu Chen Cheng
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Patent number: 8719294Abstract: A network digital creation system and the method thereof are disclosed. The client end executes a web page document embedded with a web page procedure in order to initialize the drawing block in the web page document and to allow the user to directly use the cursor to draw. It further enables the user to use quote images previously stored in the server end or the quote the graphic resources in the external network for drawing. After finishing the plot, the user stores the result to the server end to become a quote image. It can be shared to other users by quoting. This facilitates the interactions of network digital creations.Type: GrantFiled: March 12, 2010Date of Patent: May 6, 2014Assignee: Fiitotech Company LimitedInventors: Hsu Chen Cheng, Yee Chiang Heng, Chia Ching Chou, Tsung Hwa Chang
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Patent number: 8213220Abstract: The present disclosure provides a non-volatile memory device. A memory device includes a first magnetic element having a fixed magnetization. The memory device also includes a second magnetic element having a non-fixed magnetization. The memory device further includes a barrier layer between the first and second magnetic elements. A unidirectional current source is electrically coupled to the first and second magnetic elements. The current source is configured to provide a first current to the first and second memory elements. The first current has a first current density and is in a first direction. The current source is also configured to provide a second current to the first and second magnetic elements. The second current has a second current density, different than the first current density, and is in the first direction.Type: GrantFiled: January 14, 2010Date of Patent: July 3, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Jen Wang, Hsu-Chen Cheng, Denny Tang
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Patent number: 8120947Abstract: The present disclosure provides a magnetic memory element. The memory element includes a magnetic tunnel junction (MTJ) element and an electrode. The electrode includes a pinning layer, a pinned layer, and a non-magnetic conductive layer. In one embodiment, the MTJ element includes a first surface having a first surface area, and the electrode includes a second surface. In the embodiment, the second surface of the electrode is coupled to the first surface of the MTJ element such that an interface area is formed and the interface area is less than the first surface area.Type: GrantFiled: August 6, 2009Date of Patent: February 21, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Jen Wang, Denny Tang, Hsu-Chen Cheng
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Patent number: 8110881Abstract: A MRAM cell structure includes a bottom electrode; a magnetic tunnel junction unit disposed on the bottom electrode; a top electrode disposed on the magnetic tunnel junction unit; and a blocking layer disposed on the top electrode, wherein the blocking layer is wider than the magnetic tunnel junction unit for preventing against formation of a short circuit between a contact and the magnetic tunnel junction unit.Type: GrantFiled: September 27, 2007Date of Patent: February 7, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ya-Chen Kao, Chun-Jung Lin, Yu-Jen Wang, Hsu-Chen Cheng, Feng-Jia Shiu, Yung-Tao Lin
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Publication number: 20110225179Abstract: A network digital creation system and the method thereof are disclosed. The client end executes a web page document embedded with a web page procedure in order to initialize the drawing block in the web page document and to allow the user to directly use the cursor to draw. It further enables the user to use quote images previously stored in the server end or the quote the graphic resources in the external network for drawing. After finishing the plot, the user stores the result to the server end to become a quote image. It can be shared to other users by quoting. This facilitates the interactions of network digital creations.Type: ApplicationFiled: March 12, 2010Publication date: September 15, 2011Applicant: Fiitotech Company LimitedInventors: Hsu Chen Cheng, Yee Chiang Heng, Chia Ching Chou, Tsung Hwa Chang
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Patent number: 7964900Abstract: A semiconductor substrate includes semi-insulating portions beneath openings in a patterned hardmask film formed over a semiconductor substructure to a thickness sufficient to prevent charged particles from passing through the hardmask. The semi-insulating portions include charged particles and may extend deep into the semiconductor substrate and electrically insulate devices formed on opposed sides of the semi-insulating portions. The charged particles may advantageously be protons and further substrate portions covered by the patterned hardmask film are substantially free of the charged particles.Type: GrantFiled: September 24, 2009Date of Patent: June 21, 2011Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Wen-Chin Lin, Denny Tang, Chuan-Ying Lee, Hsu Chen Cheng
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Patent number: 7719882Abstract: Disclosed herein is a technique for created an advanced MRAM array for constructing a memory integrated circuit chip. More specifically, the disclosed principles provide for an integrated circuit memory chip comprised of a combination of at least one of an array of high-speed magnetic memory cells, and at least one of an array of high-density magnetic memory cells. Accordingly, a memory chip constructed as disclosed herein provides the benefit of both high-speed and high-density memory cells on the same memory chip. As a result, applications benefiting from the use of (or perhaps even needing) high-speed memory cells are provided by the memory cells in the high-speed memory cell array.Type: GrantFiled: May 2, 2007Date of Patent: May 18, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chin Lin, Hsu-Chen Cheng, Yu-Jen Wang, Denny Tang
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Publication number: 20100118603Abstract: The present disclosure provides a non-volatile memory device. A memory device includes a first magnetic element having a fixed magnetization. The memory device also includes a second magnetic element having a non-fixed magnetization. The memory device further includes a barrier layer between the first and second magnetic elements. A unidirectional current source is electrically coupled to the first and second magnetic elements. The current source is configured to provide a first current to the first and second memory elements. The first current has a first current density and is in a first direction. The current source is also configured to provide a second current to the first and second magnetic elements. The second current has a second current density, different than the first current density, and is in the first direction.Type: ApplicationFiled: January 14, 2010Publication date: May 13, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Jen Wang, Hsu-Chen Cheng, Denny Tang
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Publication number: 20090290410Abstract: The present disclosure provides a magnetic memory element. The memory element includes a magnetic tunnel junction (MTJ) element and an electrode. The electrode includes a pinning layer, a pinned layer, and a non-magnetic conductive layer. In one embodiment, the MTJ element includes a first surface having a first surface area, and the electrode includes a second surface. In the embodiment, the second surface of the electrode is coupled to the first surface of the MTJ element such that an interface area is formed and the interface area is less than the first surface area.Type: ApplicationFiled: August 6, 2009Publication date: November 26, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Jen Wang, Denny Tang, Hsu-Chen Cheng
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Patent number: 7622358Abstract: A method for forming semi-insulating portions in a semiconductor substrate provides depositing a hardmask film over a semiconductor substructure to a thickness sufficient to prevent charged particles from passing through the hardmask. The hardmask is patterned creating openings through which charged particles pass and enter the substrate during an implantation process. The semi-insulating portions may extend deep into the semiconductor substrate and electrically insulate devices formed on opposed sides of the semi-insulating portions. The charged particles may advantageously be protons and further substrate portions covered by the patterned hardmask film are substantially free of the charged particles.Type: GrantFiled: September 30, 2005Date of Patent: November 24, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Chin Lin, Denny Tang, Chuan-Ying Lee, Hsu Chen Cheng
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Patent number: 7599215Abstract: Disclosed herein are toggle-mode magnetoresistive random access memory (MRAM) devices having small-angle toggle write lines, and related methods of toggle-mode switching MRAM devices. Also disclosed are layouts for MRAM devices constructed according to the disclosed principles. Generally speaking, the disclosed principles provide for non-orthogonally aligned toggle-mode write lines used to switch toggle-mode MRAM devices that employ a bias field to decrease the threshold needed to switch the magnetic state of each device. While the conventional toggle-mode write lines provide for the desired orthogonal orientation of the applied magnetic fields to optimize device switching, the use of a bias field affects this orthogonal orientation. By non-orthogonally aligning the two write lines as disclosed herein, the detrimental affect of the bias field may be compensated for such that the net fields applied to the device for both lines are again substantially orthogonal, as is desired.Type: GrantFiled: August 16, 2007Date of Patent: October 6, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chin Lin, Denny Tang, Hsu Chen Cheng
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Patent number: 7573736Abstract: The present disclosure provides a magnetic memory element. The memory element includes a magnetic tunnel junction (MTJ) element and an electrode. The electrode includes a pinning layer, a pinned layer, and a non-magnetic conductive layer. In one embodiment, the MTJ element includes a first surface having a first surface area, and the electrode includes a second surface. In the embodiment, the second surface of the electrode is coupled to the first surface of the MTJ element such that an interface area is formed and the interface area is less than the first surface area.Type: GrantFiled: May 22, 2007Date of Patent: August 11, 2009Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yu-Jen Wang, Denny Tang, Hsu-Chen Cheng
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Publication number: 20090085132Abstract: A MRAM cell structure includes a bottom electrode; a magnetic tunnel junction unit disposed on the bottom electrode; a top electrode disposed on the magnetic tunnel junction unit; and a blocking layer disposed on the top electrode, wherein the blocking layer is wider than the magnetic tunnel junction unit for preventing against formation of a short circuit between a contact and the magnetic tunnel junction unit.Type: ApplicationFiled: September 27, 2007Publication date: April 2, 2009Inventors: Ya Chen Kao, Chun-Jung Lin, Yu-Jen Wang, Hsu-Chen Cheng, Feng-Jia Shiu, Yung-Tao Lin
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Publication number: 20080291720Abstract: The present disclosure provides a magnetic memory element. The memory element includes a magnetic tunnel junction (MTJ) element and an electrode. The electrode includes a pinning layer, a pinned layer, and a non-magnetic conductive layer. In one embodiment, the MTJ element includes a first surface having a first surface area, and the electrode includes a second surface. In the embodiment, the second surface of the electrode is coupled to the first surface of the MTJ element such that an interface area is formed and the interface area is less than the first surface area.Type: ApplicationFiled: May 22, 2007Publication date: November 27, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Jen Wang, Denny Tang, Hsu-Chen Cheng
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Publication number: 20080239794Abstract: Disclosed herein are toggle-mode magnetoresistive random access memory (MRAM) devices having small-angle toggle write lines, and related methods of toggle-mode switching MRAM devices. Also disclosed are layouts for MRAM devices constructed according to the disclosed principles. Generally speaking, the disclosed principles provide for non-orthogonally aligned toggle-mode write lines used to switch toggle-mode MRAM devices that employ a bias field to decrease the threshold needed to switch the magnetic state of each device. While the conventional toggle-mode write lines provide for the desired orthogonal orientation of the applied magnetic fields to optimize device switching, the use of a bias field affects this orthogonal orientation. By non-orthogonally aligning the two write lines as disclosed herein, the detrimental affect of the bias field may be compensated for such that the net fields applied to the device for both lines are again substantially orthogonal, as is desired.Type: ApplicationFiled: August 16, 2007Publication date: October 2, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wen-Chin Lin, Denny Tang, Hsu-Chen Cheng
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Publication number: 20080186757Abstract: Disclosed herein is a technique for created an advanced MRAM array for constructing a memory integrated circuit chip. More specifically, the disclosed principles provide for an integrated circuit memory chip comprised of a combination of at least one of an array of high-speed magnetic memory cells, and at least one of an array of high-density magnetic memory cells. Accordingly, a memory chip constructed as disclosed herein provides the benefit of both high-speed and high-density memory cells on the same memory chip. As a result, applications benefiting from the use of (or perhaps even needing) high-speed memory cells are provided by the memory cells in the high-speed memory cell array.Type: ApplicationFiled: May 2, 2007Publication date: August 7, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wen-Chin Lin, Hsu-Chen Cheng, Yu-Jen Wang, Denny Tang
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Patent number: 7349243Abstract: Disclosed herein are various embodiments of a 3-parameter switching technique for MRAM memory cells arranged on an MRAM array. The disclosed technique alters the relationship between the disturbance margin and write margin of MRAM arrays to reduce the overall disturbance for the arrays by either enlarging the write margin with respect to the original disturbance margin or enlarging the disturbance margin in view of the original write margin. In either approach, the disclosed 3-parameter switching technique successfully decreases the inadvertent writing of unselected bits.Type: GrantFiled: April 20, 2006Date of Patent: March 25, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chin Lin, Denny Tang, Hsu-Chen Cheng