Patents by Inventor Hsu-Chi Cho

Hsu-Chi Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10896911
    Abstract: A method for forming a memory device is provided. The method includes forming a floating gate on a substrate, and forming a control gate on the floating gate. The method also includes forming a mask layer on the control gate, and forming a spacer on a sidewall of the mask layer, wherein a sidewall of the control gate and a sidewall of the floating gate is covered by the spacer. The method further includes performing an ion implantation process to implant a dopant into a top portion of the spacer, and performing a wet etching process to expose the sidewall of the control gate.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: January 19, 2021
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Hsu-Chi Cho, Cheng-Ta Yang
  • Publication number: 20190348426
    Abstract: A method for forming a memory device is provided. The method includes forming a floating gate on a substrate, and forming a control gate on the floating gate. The method also includes forming a mask layer on the control gate, and forming a spacer on a sidewall of the mask layer, wherein a sidewall of the control gate and a sidewall of the floating gate is covered by the spacer. The method further includes performing an ion implantation process to implant a dopant into a top portion of the spacer, and performing a wet etching process to expose the sidewall of the control gate.
    Type: Application
    Filed: April 3, 2019
    Publication date: November 14, 2019
    Inventors: Hsu-Chi CHO, Cheng-Ta YANG
  • Patent number: 10157930
    Abstract: A method for fabricating a memory device is provided. In the method, a first gate dielectric layer is formed on a substrate in a first region. A second gate dielectric layer is formed on the substrate in a second region and a third region. A first conductive layer is formed on the substrate. A first dielectric layer is directly formed on the first conductive layer. One portion of the first dielectric layer, one portion of the first conductive layer, and one portion of the second gate dielectric layer in the second region are removed. A third gate dielectric layer and a second conductive layer are formed sequentially on the substrate in the second region. A third conductive layer and a second dielectric layer are formed sequentially on the substrate. Isolation structures are formed in the substrate. Here, the isolation structures penetrate the second dielectric layer and extend into the substrate.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: December 18, 2018
    Assignee: Winbond Electronics Corp.
    Inventors: Chun-Hsu Chen, Hsu-Chi Cho
  • Publication number: 20180061848
    Abstract: A method for fabricating a memory device is provided. In the method, a first gate dielectric layer is formed on a substrate in a first region. A second gate dielectric layer is formed on the substrate in a second region and a third region. A first conductive layer is formed on the substrate. A first dielectric layer is directly formed on the first conductive layer. One portion of the first dielectric layer, one portion of the first conductive layer, and one portion of the second gate dielectric layer in the second region are removed. A third gate dielectric layer and a second conductive layer are formed sequentially on the substrate in the second region. A third conductive layer and a second dielectric layer are formed sequentially on the substrate. Isolation structures are formed in the substrate. Here, the isolation structures penetrate the second dielectric layer and extend into the substrate.
    Type: Application
    Filed: November 16, 2016
    Publication date: March 1, 2018
    Applicant: Winbond Electronics Corp.
    Inventors: Chun-Hsu Chen, Hsu-Chi Cho