Patents by Inventor Hsu Chiang

Hsu Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210265280
    Abstract: A semiconductor device package includes an electronic component, an electrical contact and a reinforcement layer. The electronic component has a first conductive layer on a first surface of the electronic component. The electronic component has a through-silicon-via (TSV) penetrating the electronic component and electrically connected to the first conductive layer. The electrical contact is disposed on the first surface of the electronic component and electrically connected to the first conductive layer. The reinforcement layer is disposed on the first surface of the electronic component.
    Type: Application
    Filed: February 21, 2020
    Publication date: August 26, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Chiang SHIH, Hung-Yi LIN, Meng-Wei HSIEH, Yu Sheng CHANG, Hsiu-Chi LIU, Mark GERBER
  • Patent number: 11062984
    Abstract: A semiconductor device includes a substrate, and interposer layers. The substrate has a first region, and a second region adjacent the first region. The interposer layers are sequentially stacked on the substrate. Each of the interposer layers has an active region and an open region, are respectively correspond to the first region and the second region of the substrate. Each of the interposer layers includes a device layout pattern, and a stress release structure. The device layout pattern is formed within the active region. The stress release structure is formed within the open region, and includes openings.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: July 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Tzung-Han Lee, Yaw-Wen Hu, Neng-Tai Shih, Hsu Chiang, Hsin-Chuan Tsai, Sheng-Hsiung Wu
  • Patent number: 11037846
    Abstract: A semiconductor package structure includes a substrate, a die electrically connected to the substrate, and a first encapsulant. The die has a front surface and a back surface opposite to the front surface. The first encapsulant is disposed between the substrate and the front surface of the die. The first encapsulant contacts the front surface of the die and the substrate.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: June 15, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Hua Chen, Hsu-Chiang Shih, Cheng-Yuan Kung, Hung-Yi Lin
  • Publication number: 20210090965
    Abstract: A semiconductor package structure includes a substrate, a die electrically connected to the substrate, and a first encapsulant. The die has a front surface and a back surface opposite to the front surface. The first encapsulant is disposed between the substrate and the front surface of the die. The first encapsulant contacts the front surface of the die and the substrate.
    Type: Application
    Filed: September 20, 2019
    Publication date: March 25, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien-Hua CHEN, Hsu-Chiang SHIH, Cheng-Yuan KUNG, Hung-Yi LIN
  • Patent number: 10818536
    Abstract: A package structure and a method for fabricating thereof are provided. The package structure includes a substrate, a first connector, a redistribution layer, a second connector, and a chip. The first connector is disposed over the substrate. The redistribution layer is directly disposed over the first connector, and is connected to the substrate by the first connector. The redistribution layer includes a block layer, and a metal layer over the block layer. The second connector is directly disposed over the redistribution layer, and the chip is connected to the redistribution layer by the second connector.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: October 27, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Shing-Yih Shih, Hsu Chiang, Neng-Tai Shih
  • Patent number: 10811420
    Abstract: The present disclosure provides a semiconductor structure and a method for forming the semiconductor structure. The semiconductor structure includes: a polysilicon layer, having a first surface and a second surface opposite to the first surface; a substrate, disposed on the second surface of the polysilicon layer; a bit line structure, disposed on the substrate, penetrating through the polysilicon layer and protruding from the first surface of the polysilicon layer; and a spacer structure, disposed on lateral sidewalls of the bit line structure, including an air gap sandwiched by a first dielectric layer and a second dielectric layer, wherein a first portion of the second dielectric layer is in the polysilicon layer, a second portion of the second dielectric layer is outside the polysilicon layer, and a thickness of the second portion of the second dielectric layer is less than a thickness of the first portion of the second dielectric layer.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: October 20, 2020
    Assignee: Nanya Technology Corporation
    Inventors: Szu-Han Chen, Hsu Chiang, Ching-Yuan Kuo
  • Publication number: 20200308085
    Abstract: This disclosure provides improved processes for converting aromatic hydrocarbons, such as benzene/toluene, alkylation, transalkylation, or isomerization. In an embodiment, a process comprises utilizing a passivated reactor to reduce deactivation of a molecular sieve catalyst. Additional measures such as the use of an auxiliary catalyst and/or an elevated reactor pressure may be used to further reduce deactivation of the molecular sieve catalyst.
    Type: Application
    Filed: March 16, 2020
    Publication date: October 1, 2020
    Inventors: Seth M. Washburn, Hsu Chiang, Umar Aslam, Wenyih Frank Lai, Doron Levin, Tan-Jen Chen
  • Publication number: 20200184061
    Abstract: The invention provides an identity authentication system and a method thereof. Embodiments of the invention provide application, installation, and verification processes of a mobile identification card, and enable a mobile apparatus of a user to be a carrier of the mobile identification card. The mobile identification card can be applied to services related to internal identification of enterprises, groups, or government agencies, and achieve smart and mobile identification. The mobile identification card is provided via an over-the-air mechanism. A mobile enterprise identification card service is provided to one or more enterprises by using a gateway. In addition, in combination with advantages of a dynamic graphics coding technology, a geographic location, data encryption with a key, transaction time recording, and other technologies, a graphic code can be generated for identity authentication. Therefore, highly secure identity authentication can be provided by using a dynamic graphic code.
    Type: Application
    Filed: December 4, 2019
    Publication date: June 11, 2020
    Applicant: Chunghwa Telecom Co., Ltd.
    Inventors: Jia-Jiun Hung, Hong-Jen Chang, Yen-Hsu Chiang, Yeou-Fuh Kuan, Char-Shin Miou
  • Publication number: 20200168497
    Abstract: A package structure and a method for fabricating thereof are provided. The package structure includes a substrate, a first connector, a redistribution layer, a second connector, and a chip. The first connector is disposed over the substrate. The redistribution layer is directly disposed over the first connector, and is connected to the substrate by the first connector. The redistribution layer includes a block layer, and a metal layer over the block layer. The second connector is directly disposed over the redistribution layer, and the chip is connected to the redistribution layer by the second connector.
    Type: Application
    Filed: January 29, 2020
    Publication date: May 28, 2020
    Inventors: Shing-Yih Shih, Hsu Chiang, Neng-Tai Shih
  • Publication number: 20200168613
    Abstract: The present disclosure provides a semiconductor structure and a method for forming the semiconductor structure. The semiconductor structure includes: a polysilicon layer, having a first surface and a second surface opposite to the first surface; a substrate, disposed on the second surface of the polysilicon layer; a bit line structure, disposed on the substrate, penetrating through the polysilicon layer and protruding from the first surface of the polysilicon layer; and a spacer structure, disposed on lateral sidewalls of the bit line structure, including an air gap sandwiched by a first dielectric layer and a second dielectric layer, wherein a first portion of the second dielectric layer is in the polysilicon layer, a second portion of the second dielectric layer is outside the polysilicon layer, and a thickness of the second portion of the second dielectric layer is less than a thickness of the first portion of the second dielectric layer.
    Type: Application
    Filed: July 3, 2019
    Publication date: May 28, 2020
    Inventors: SZU-HAN CHEN, HSU CHIANG, CHING-YUAN KUO
  • Publication number: 20200152639
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a base and a plurality of protrusions extending from the base and spaced apart from each other; a first oxide layer substantially disposed between two adjacent protrusions and exposing an upper portion of the protrusion between portions of the first oxide layer; a bit line contact covering the upper portion of the protrusion; a bit line disposed over the bit line contact; a first nitride layer disposed on lateral surfaces of the bit line contact and the bit line and on an upper surface and a sidewall of the first oxide layer exposed to the bit line contact; and a second nitride layer at least formed over the first nitride layer disposed on the lateral surfaces with an interval and connected to the first nitride layer disposed on the sidewall, thereby forming an air gap between the first and second nitride layers.
    Type: Application
    Filed: November 8, 2018
    Publication date: May 14, 2020
    Inventors: Jui-Wen HO, Hsu CHIANG, Szu-Han CHEN
  • Patent number: 10566229
    Abstract: A package structure and a method for fabricating thereof are provided. The package structure includes a substrate, a first connector, a redistribution layer, a second connector, and a chip. The first connector is disposed over the substrate. The redistribution layer is directly disposed over the first connector, and is connected to the substrate by the first connector. The redistribution layer includes a block layer, and a metal layer over the block layer. The second connector is directly disposed over the redistribution layer, and the chip is connected to the redistribution layer by the second connector.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: February 18, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Shing-Yih Shih, Hsu Chiang, Neng-Tai Shih
  • Patent number: 10304765
    Abstract: A semiconductor device package includes a substrate, a first insulation layer, a support film and an interconnection structure. The substrate has a first sidewall, a first surface and a second surface opposite to the first surface. The first insulation layer is on the first surface of the substrate and has a second sidewall. The first insulation layer has a first surface and a second surface adjacent to the substrate and opposite to the first surface of the first insulation layer. The support film is on the second surface of the substrate and has a third sidewall. The support film has a first surface adjacent to the substrate and a second surface opposite to the first surface of the support film. The interconnection structure extends from the first surface of the first insulation layer to the second surface of the support film via the first insulation layer and the support film. The interconnection structure covers the first, second and third sidewalls.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: May 28, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Hua Chen, Ming-Hung Chen, Hsu-Chiang Shih
  • Publication number: 20190074246
    Abstract: A semiconductor device includes a substrate, and interposer layers. The substrate has a first region, and a second region adjacent the first region. The interposer layers are sequentially stacked on the substrate. Each of the interposer layers has an active region and an open region, are respectively correspond to the first region and the second region of the substrate. Each of the interposer layers includes a device layout pattern, and a stress release structure. The device layout pattern is formed within the active region. The stress release structure is formed within the open region, and includes openings.
    Type: Application
    Filed: November 1, 2018
    Publication date: March 7, 2019
    Inventors: Tzung-Han Lee, Yaw-Wen Hu, Neng-Tai Shih, Hsu Chiang, Hsin-Chuan Tsai, Sheng-Hsiung Wu
  • Publication number: 20180358290
    Abstract: A semiconductor device package includes a substrate, a first insulation layer, a support film and an interconnection structure. The substrate has a first sidewall, a first surface and a second surface opposite to the first surface. The first insulation layer is on the first surface of the substrate and has a second sidewall. The first insulation layer has a first surface and a second surface adjacent to the substrate and opposite to the first surface of the first insulation layer. The support film is on the second surface of the substrate and has a third sidewall. The support film has a first surface adjacent to the substrate and a second surface opposite to the first surface of the support film. The interconnection structure extends from the first surface of the first insulation layer to the second surface of the support film via the first insulation layer and the support film. The interconnection structure covers the first, second and third sidewalls.
    Type: Application
    Filed: June 8, 2017
    Publication date: December 13, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien-Hua CHEN, Ming-Hung CHEN, Hsu-Chiang SHIH
  • Publication number: 20180349885
    Abstract: The invention provides a mobile device, a method, a computer program product, and an issuance system for configuring a ticket co-branded credit card based on tokenization technology. The method includes the following steps. The mobile device is communication connected to a token service provider (TSP) and a trusted service manager (TSM). The TSP connects to a card issuer, and the TSM connects to a ticket issuer. Next, the mobile device transmits a ticket co-branded credit card request to the TSP so as to trigger the TSP to return a corresponding credit card token, and a ticket co-branding request is submitted to the ticket issuer via the card issuer, so that the ticket issuer returns an electronic ticket associated with the credit card token via the TSM. Through the above operation, security and convenience in use of a credit card can be effectively enhanced.
    Type: Application
    Filed: September 15, 2017
    Publication date: December 6, 2018
    Applicant: Chunghwa Telecom Co., Ltd.
    Inventors: Yih-Chyau Kuo, Cheng-Chun Yu, Hong-Jen Chang, Yen-Hsu Chiang, Yeou-Fuh Kuan, Char-Shin Miou
  • Patent number: 10121734
    Abstract: A semiconductor device includes a substrate, and interposer layers. The substrate has a first region, and a second region adjacent the first region. The interposer layers are sequentially stacked on the substrate. Each of the interposer layers has an active region and an open region, which respectively correspond to the first region and the second region of the substrate. Each of the interposer layers includes a device layout pattern, and a stress release structure. The device layout pattern is formed within the active region. The stress release structure is formed within the open region, and includes openings.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: November 6, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Tzung-Han Lee, Yaw-Wen Hu, Neng-Tai Shih, Hsu Chiang, Hsin-Chuan Tsai, Sheng-Hsiung Wu
  • Publication number: 20180190761
    Abstract: A metal-insulator-metal (MIM) capacitor is disclosed. The MIM capacitor includes a substrate having a first dielectric layer thereon and a bottom electrode embedded in the first dielectric layer. The bottom electrode includes a metal plate and a three-dimensional (3D) metal structure protruding from a top surface of the metal plate. A second dielectric layer surrounds the 3D metal structure. A capacitor dielectric layer covers the 3D metal structure and the second dielectric layer. A top electrode is disposed on the capacitor dielectric layer. The top electrode has fins that interdigitate with the 3D metal structure.
    Type: Application
    Filed: January 3, 2017
    Publication date: July 5, 2018
    Inventors: Hsu Chiang, Neng-Tai Shih, Tieh-Chiang Wu
  • Publication number: 20180190531
    Abstract: A package structure and a method for fabricating thereof are provided. The package structure includes a substrate, a first connector, a redistribution layer, a second connector, and a chip. The first connector is disposed over the substrate. The redistribution layer is directly disposed over the first connector, and is connected to the substrate by the first connector. The redistribution layer includes a block layer, and a metal layer over the block layer. The second connector is directly disposed over the redistribution layer, and the chip is connected to the redistribution layer by the second connector.
    Type: Application
    Filed: March 2, 2018
    Publication date: July 5, 2018
    Inventors: Shing-Yih Shih, Hsu Chiang, Neng-Tai Shih
  • Patent number: 9916999
    Abstract: A package structure and a method for fabricating thereof are provided. The package structure includes a substrate, a first connector, a redistribution layer, a second connector, and a chip. The first connector is disposed over the substrate. The redistribution layer is directly disposed over the first connector, and is connected to the substrate by the first connector. The redistribution layer includes a block layer, and a metal layer over the block layer. The second connector is directly disposed over the redistribution layer, and the chip is connected to the redistribution layer by the second connector.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: March 13, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Shing-Yih Shih, Hsu Chiang, Neng-Tai Shih