Patents by Inventor Hsu-Chieh Cheng

Hsu-Chieh Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230015372
    Abstract: A method includes forming a fin protruding from a substrate, forming a first dielectric feature adjacent to the fin over the substrate, forming a cladding layer over the fin and the first dielectric feature, and removing a portion of the cladding layer to form an opening. The opening exposes the first dielectric feature. The method further includes forming a second dielectric feature adjacent to the cladding layer, the second dielectric feature filling the opening, forming a dummy gate stack over the fin and the second dielectric feature, forming source/drain (S/D) features in the fin adjacent to the dummy gate stack, and replacing the dummy gate stack and the cladding layer with a metal gate stack. The second dielectric feature divides the metal gate stack.
    Type: Application
    Filed: May 4, 2022
    Publication date: January 19, 2023
    Inventors: Ming-Yuan Wu, Da-Wen Lin, Yi-Ting Fu, Hsu-Chieh Cheng, Min Jiao
  • Patent number: 10707331
    Abstract: A method includes forming a fin structure on a substrate, forming a dummy gate structure wrapped around the fin structure, depositing an Interlayer Dielectric (ILD) layer over the fin structure, removing the dummy gate structure to expose a portion of the fin structure, and performing an etching process on the portion of the fin structure to reduce a width of the portion of the fin structure.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: July 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ka-Hing Fung, Chen-Yu Hsieh, Che-Yuan Hsu, Ming-Yuan Wu, Hsu-Chieh Cheng
  • Publication number: 20180315837
    Abstract: A method includes forming a fin structure on a substrate, forming a dummy gate structure wrapped around the fin structure, depositing an Interlayer Dielectric (ILD) layer over the fin structure, removing the dummy gate structure to expose a portion of the fin structure, and performing an etching process on the portion of the fin structure to reduce a width of the portion of the fin structure.
    Type: Application
    Filed: April 28, 2017
    Publication date: November 1, 2018
    Inventors: Ka-Hing Fung, Chen-Yu Hsieh, Che-Yuan Hsu, Ming-Yuan Wu, Hsu-Chieh Cheng