Patents by Inventor Hsu-Chih Chiang

Hsu-Chih Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9772937
    Abstract: A data processing method, a memory controller and a memory storage apparatus are provided. The method includes receiving a write command from a host system. A write data stream corresponding to the write command includes multiple sub-data streams, and each of the sub-data streams is attached with a data index mark by an application installed in the host system. The application determines the data index mark attached to each sub-data stream in accordance with a first rule including a predetermined function, an initial parameter selecting manner and a parameter increasing manner, in which the first rule is pre-agreed by the application with the memory storage apparatus. The method also includes reordering the sub-data streams according to the first rule and the data index mark of each sub-data stream. The method further includes transmitting the reordered sub-data streams to a smartcard chip in the memory storage apparatus.
    Type: Grant
    Filed: March 17, 2013
    Date of Patent: September 26, 2017
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Hsu-Chih Chiang
  • Patent number: 9043549
    Abstract: A memory storage apparatus, a memory controller and method for transmitting and identifying data streams are provided. The memory controller passes at least a portion of a data stream received from a host system to a smart card chip of the memory storage apparatus. Then, the host system accurately receives a response message from the smart card chip by executing a plurality of read commands. The memory controller is capable of adding a first verification code to a response data stream sent to the host system, and is capable of adding a write token to each of data segments of the response data stream. The host system confirms the accuracy of the response data stream by verifying the first verification code or by verifying the write token of each of the data segments.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: May 26, 2015
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Hsu-Chih Chiang
  • Publication number: 20140156913
    Abstract: A data processing method, a memory controller and a memory storage apparatus are provided. The method includes receiving a write command from a host system. A write data stream corresponding to the write command includes multiple sub-data streams, and each of the sub-data streams is attached with a data index mark by an application installed in the host system. The application determines the data index mark attached to each sub-data stream in accordance with a first rule including a predetermined function, an initial parameter selecting manner and a parameter increasing manner, in which the first rule is pre-agreed by the application with the memory storage apparatus. The method also includes reordering the sub-data streams according to the first rule and the data index mark of each sub-data stream. The method further includes transmitting the reordered sub-data streams to a smartcard chip in the memory storage apparatus.
    Type: Application
    Filed: March 17, 2013
    Publication date: June 5, 2014
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Hsu-Chih Chiang
  • Publication number: 20130117507
    Abstract: A memory storage apparatus, a memory controller and method for transmitting and identifying data streams are provided. The memory controller passes at least a portion of a data stream received from a host system to a smart card chip of the memory storage apparatus. Then, the host system accurately receives a response message from the smart card chip by executing a plurality of read commands. The memory controller is capable of adding a first verification code to a response data stream sent to the host system, and is capable of adding a write token to each of data segments of the response data stream. The host system confirms the accuracy of the response data stream by verifying the first verification code or by verifying the write token of each of the data segments.
    Type: Application
    Filed: January 17, 2012
    Publication date: May 9, 2013
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Hsu-Chih Chiang