Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.

Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes depositing an etch stop layer on a cobalt contact disposed on a substrate, depositing a dielectric on the etch stop layer, etching the dielectric and the etch stop layer to form an opening that exposes a top surface of the cobalt contact, and etching the exposed top surface of the cobalt contact to form a recess in the cobalt contact extending laterally under the etch stop layer. The method further includes depositing a ruthenium metal to substantially fill the recess and the opening, and annealing the ruthenium metal to form an oxide layer between the ruthenium metal and the dielectric.

Abstract: A transmitting apparatus operative at a plurality of different bands includes at least a modulator, an intermediate frequency (IF) filter, and an offset phase-locked-loop (OPLL). Regardless at which one of the frequency bands the transmitting apparatus operates, a divisor of at least one frequency divider included within the OPLL is fixed, and a signal, which is outputted by a controllable oscillator and received by an offset mixer included within the OPLL, corresponds to a substantially fixed frequency.

Abstract: An RFID chip is modified with set data before being disposed in an electronic label so as to allow the electronic label to be selectively used with different types of RFID systems. The RFID chip includes a first data storage zone for storing first data set accessible by the first type of RFID system and the second type of RFID system; and a second data storage zone for storing second data set inaccessible by the first type of RFID system and the second type of RFID system. The second data set includes a modifiable code for indicating a type of the electronic label and with which of the first type of RFID system and the second type of RFID system the electronic label is to be used.

Abstract: A phase locked loop (PLL) includes a clock generating circuit, a first phase detecting circuit, a first loop filter, a first VCO, a first mixer and a control circuit. The clock generating circuit generates a first clock signal. The first phase detecting circuit detects a phase difference between an input data signal and a feedback signal and generates a detection output signal according to the phase difference. The first loop filter, coupled to the first phase detecting circuit, generates a first VCO control signal according to the detection output signal. The first mixer, coupled to the first VCO and the clock generating circuit, mixes the output data signal and the first clock signal to generate the feedback data signal. The control circuit, coupled to the clock generating circuit and the first loop filter, for adjusting the first clock signal according to the first VCO control signal to calculate a gain of the first VCO.

Abstract: An RFID interrogator includes a signal processing module for converting a transmission signal transmitted from an RFID tag into an input signal; a first matched filter coupled to the signal processing module for generating a first matched signal according to the input signal and a first predetermined signal pattern; a second matched filter coupled to the signal processing module for generating a second matched signal according to the input signal and a second predetermined signal pattern; a control unit for generating a control signal according to the input signal; and a decision unit, coupled to the first matched filter, the second matched filter and the control unit, for comparing the first matched signal with the second matched signal according to the control signal to generate a read-back signal.

Abstract: A circuit for calibrating the DC offset in a wireless communication device utilizes a voltage-generating circuit to generate a first voltage value and its negative value, and utilizes a detecting circuit to detect an output of the wireless communication device and generate a first target-branch reference value corresponding to the power of the output when the first voltage value is inputted into a target branch (e.g., the in-phase branch or the quadrature branch) of the wireless communication device, and detect an output of the wireless communication device and generate a second target-branch reference value corresponding to the power of the output when the negative value of the first voltage value is input into the target branch. Then, an estimating circuit estimates the DC offset on the target branch according to the first and second target-branch reference values and the first voltage value.

Abstract: A transmitting apparatus operative at a plurality of different bands includes at least a modulator, an intermediate frequency (IF) filter, and an offset phase-locked-loop (OPLL). Regardless at which one of the frequency bands the transmitting apparatus operates, a divisor of at least one frequency divider included within the OPLL is fixed, and a signal, which is outputted by a controllable oscillator and received by an offset mixer included within the OPLL, corresponds to a substantially fixed frequency.

Abstract: A phase locked loop (PLL) includes a clock generating circuit, a first phase detecting circuit, a first loop filter, a first VCO, a first mixer and a control circuit. The clock generating circuit generates a first clock signal. The first phase detecting circuit detects a phase difference between an input data signal and a feedback signal and generates a detection output signal according to the phase difference. The first loop filter, coupled to the first phase detecting circuit, generates a first VCO control signal according to the detection output signal. The first mixer, coupled to the first VCO and the clock generating circuit, mixes the output data signal and the first clock signal to generate the feedback data signal. The control circuit, coupled to the clock generating circuit and the first loop filter, for adjusting the first clock signal according to the first VCO control signal to calculate a gain of the first VCO.

Abstract: A circuit for calibrating the DC offset in a wireless communication device utilizes a voltage-generating circuit to generate a first voltage value and its negative value, and utilizes a detecting circuit to detect an output of the wireless communication device and generate a first target-branch reference value corresponding to the power of the output when the first voltage value is inputted into a target branch (e.g., the in-phase branch or the quadrature branch) of the wireless communication device, and detect an output of the wireless communication device and generate a second target-branch reference value corresponding to the power of the output when the negative value of the first voltage value is input into the target branch. Then, an estimating circuit estimates the DC offset on the target branch according to the first and second target-branch reference values and the first voltage value.

Abstract: An RFID interrogator includes a signal processing module for converting a transmission signal transmitted from an RFID tag into an input signal; a first matched filter coupled to the signal processing module for generating a first matched signal according to the input signal and a first predetermined signal pattern; a second matched filter coupled to the signal processing module for generating a second matched signal according to the input signal and a second predetermined signal pattern; a control unit for generating a control signal according to the input signal; and a decision unit, coupled to the first matched filter, the second matched filter and the control unit, for comparing the first matched signal with the second matched signal according to the control signal to generate a read-back signal.

Abstract: An RFID chip is modified with set data before being disposed in an electronic label so as to allow the electronic label to be selectively used with different types of RFID systems. The RFID chip includes a first data storage zone for storing first data set accessible by the first type of RFID system and the second type of RFID system; and a second data storage zone for storing second data set inaccessible by the first type of RFID system and the second type of RFID system. The second data set includes a modifiable code for indicating a type of the electronic label and with which of the first type of RFID system and the second type of RFID system the electronic label is to be used.

Abstract: The present invention provides a computer pointing device which uses capacitors installed in various directions to generate pointing signals. The pointing device comprises a circuit board, a cap, and a detecting unit. The circuit board comprises a center point, a first conducting plate installed in a first direction and a second conducting plate installed in a second direction. The cap is movably installed above the center point of the circuit board. The bottom side of the cap has a top conducting plate which forms first and second capacitors with the first and second conducting plates separately. The detecting unit is electrically connected to the top, first and second conducting plates to detect the capacitance of the first and second capacitors and generate corresponding pointing signals to reflect the position of the cap in the first and second directions.