Abstract: A method for compressing images based on joint photographic experts group (JPEG) standard includes: compressing data of one or more first image blocks with a first compression level to produce compression data of the one or more first image blocks; adjusting the first compression level to obtain a second compression level according to at least one of a data size-related index regarding the compression data of the one or more first image blocks or a transmission-related index regarding transmission of the compression data of the one or more first image blocks; and compressing data of a second image block with the second compression level.

Abstract: Disclosed is a data processing device including a main SoC, a performance-enhancing SoC, and an external circuit that is set outside any of the two SoCs. The main SoC includes: a first central processing unit (CPU) dividing to-be-processed data into a first input part and a second input part, and processing the first input part to generate first output data; and a first transceiver circuit forwarding the second input part to the performance-enhancing SoC via the external circuit, and then receiving second output data via the external circuit and forwarding it. The performance-enhancing SoC includes: a second transceiver circuit receiving the second input part via the external circuit, and transmitting the second output data to the main SoC via the external circuit; and a second CPU receiving the second input part from the second transceiver circuit and processing it to provide the second output data for the second transceiver circuit.

Abstract: The present disclosure discloses an image processing circuit having output timing adjustment mechanism. An image enhancement circuit performs image enhancement on an input image to generate an enhanced image. A first image processing path and a second image processing path respectively perform processing on the enhanced image having a first timing and the enhanced image having a second timing to generate a first output image and a second output image. A timing control circuit adjusts the timing of the enhanced image according to requirements of the first image processing path and the second image processing path to generate the enhanced image having the first timing and the enhanced image having the second timing. A first image output interface outputs the first output image. A second image output interface outputs the second output image.

Abstract: Disclosed is a graphics processing device including a main SoC, a performance-enhancing SoC, and an external circuit that is set outside any of the two SoCs. The main SoC includes: a first graphics processing unit (GPU) dividing to-be-processed data into a first input part and a second input part, and processing the first output part to generate first output data; and a first transceiver circuit forwarding the second input part to the performance-enhancing SoC via the external circuit, and then receiving second output data via the external circuit and forwarding it. The performance-enhancing SoC includes: a second transceiver circuit receiving the second input part via the external circuit and outputting the second output data to the main SoC via the external circuit; and a second GPU receiving the second input part from the second transceiver circuit and processing this part to provide the second output data for the second transceiver.

Abstract: A receiver decoding apparatus includes a first receiver decoder, a demultiplexer, a first receiver encoder and a second receiver decoder. The first receiver decoder decodes a plurality of N-bit code words received from a transmitter encoding apparatus to generate a plurality of I-bit code words, wherein N and I are both positive integers and N is not equal to I. The demultiplexer alternately deinterleaves and assigns the plurality of I-bit code words to a plurality of output terminals of the demultiplexer. The first receiver encoder encodes a plurality of outputs of the output terminals of the demultiplexer to a fifth digital signal comprising a plurality of J-bit code words and a sixth digital signal comprising a plurality of J-bit code words, wherein J is a positive integer and not equal to I. The second receiver decoder decodes the fifth digital signal and the sixth digital signal.

Abstract: A method for compressing images based on joint photographic experts group (JPEG) standard includes: compressing data of one or more first image blocks with a first compression level to produce compression data of the one or more first image blocks; adjusting the first compression level to obtain a second compression level according to at least one of a data size-related index regarding the compression data of the one or more first image blocks or a transmission-related index regarding transmission of the compression data of the one or more first image blocks; and compressing data of a second image block with the second compression level.

Abstract: A receiver decoding apparatus includes a first receiver decoder, a demultiplexer, a first receiver encoder and a second receiver decoder. The first receiver decoder decodes a plurality of N-bit code words received from a transmitter encoding apparatus to generate a plurality of I-bit code words, wherein N and I are both positive integers and N is not equal to I. The demultiplexer alternately deinterleaves and assigns the plurality of I-bit code words to a plurality of output terminals of the demultiplexer. The first receiver encoder encodes a plurality of outputs of the output terminals of the demultiplexer to a fifth digital signal comprising a plurality of J-bit code words and a sixth digital signal comprising a plurality of J-bit code words, wherein J is a positive integer and not equal to I. The second receiver decoder decodes the fifth digital signal and the sixth digital signal.

Abstract: The electronic device with power-off partition includes a signal transmitting module, two repeater modules, and a working module. Each of the repeater modules includes a first power domain, a second power domain, and a transceiver circuit. A transmission path between the first power domain and the second power domain is maintained at a logic state when the second power domain is in power off mode. The transceiver circuit of one of the two repeater modules encodes a standby signal obtained from the signal transmitting module and transmits an encoded standby signal. The transceiver circuit of the other of the repeater modules decodes the encoded standby signal and transmits a decoded standby signal. The working module transmits, according to the decoded standby signal, a power-off signal to the transceiver circuits of the two repeater modules, so that the second power domains enter the power-off mode in response to the power-off signal.

Abstract: A split-type display system includes a processing device, a display device, and a transmission cable connecting the devices. The processing device includes a processing unit and a low-to-high unit. The processing unit generates a first image signal having both a first transmission rate and a first channel number. The low-to-high unit converts the first image signal into a second image signal having both a second transmission rate and a second channel number. The first transmission rate is lower than the second transmission rate. The display device includes a high-to-low unit and a display unit. The high-to-low unit receives and converts the second image signal into a third image signal having both a third transmission rate and a third channel number. The display unit displays the third image signal. a number of channels of the transmission cable is the same as the second channel number.

Abstract: A transmitter encoding apparatus includes a multiplexer and a first transmitter encoder. The multiplexer receives a first digital signal and a second signal and to generate an output, in which the output of the multiplexer includes M-bit code words of the first digital signal and M-bit code words of the second digital signal arranged in an interleaved manner. The first transmitter encoder receives the output of the multiplexer and generates N-bit code words, and N is not equal to M. The first transmitter encoder determines a current N-bit code word of the N-bit code words according to the output of the multiplexer and a disparity of a previous N-bit code word of the N-bit code words. The first transmitter encoder transmits the N-bit code words to a receiver decoding apparatus including a demultiplexer and a first receiver decoder configured to decode the N-bit code words.

Abstract: An image processing device includes a main SoC, an performance-enhancing SoC, and an external circuit set outside any of the two SoCs. The main SoC includes: a data splitter dividing input image data into a first input part and a second input part; a first image processing circuit processing the first input part to generate a first output part; and a transmitter outputting the second input part to the performance-enhancing SoC via the external circuit. The performance-enhancing SoC includes: a receiver receiving the second input part via the external circuit; and a second image processing circuit processing the second input part to generate a second output part. The combination of the two output parts jointly determines a data amount per unit of time which exceeds the processing capability of any of the two image processing circuits. Each of the two SoCs includes a CPU, and the two CPUs cooperate, too.

Abstract: A split-type display system includes a processing device, a display device, and a transmission cable connecting the processing device and the displaying device. The processing device includes a processing unit, a first and a second conversion unit. The display device includes a third and a fourth conversion unit, and a display unit. The processing unit generates a first image signal and a first timing control signal. The first and the second conversion units, respectively, converts the first image signal and the first timing control signal into a second image signal and a second timing control signal. The third and the fourth conversion units, respectively, receive and convert the second image signal and the second timing control signal into a third image signal and a third timing control signal. The display unit displays the third image signal according to the third timing control signal.

Abstract: A transmitter encoding apparatus includes a multiplexer and a first transmitter encoder. The multiplexer receives a first digital signal and a second signal and to generate an output, in which the output of the multiplexer includes M-bit code words of the first digital signal and M-bit code words of the second digital signal arranged in an interleaved manner. The first transmitter encoder receives the output of the multiplexer and generates N-bit code words, and N is not equal to M. The first transmitter encoder determines a current N-bit code word of the N-bit code words according to the output of the multiplexer and a disparity of a previous N-bit code word of the N-bit code words. The first transmitter encoder transmits the N-bit code words to a receiver decoding apparatus including a demultiplexer and a first receiver decoder configured to decode the N-bit code words.

Abstract: The electronic device with power-off partition includes a signal transmitting module, two repeater modules, and a working module. Each of the repeater modules includes a first power domain, a second power domain, and a transceiver circuit. A transmission path between the first power domain and the second power domain is maintained at a logic state when the second power domain is in power off mode. The transceiver circuit of one of the two repeater modules encodes a standby signal obtained from the signal transmitting module and transmits an encoded standby signal. The transceiver circuit of the other of the repeater modules decodes the encoded standby signal and transmits a decoded standby signal. The working module transmits, according to the decoded standby signal, a power-off signal to the transceiver circuits of the two repeater modules, so that the second power domains enter the power-off mode in response to the power-off signal.

Abstract: A split-type display system includes a processing device, a display device, and a transmission cable connecting the processing device and the displaying device. The processing device includes a processing unit, a first and a second conversion unit. The display device includes a third and a fourth conversion unit, and a display unit. The processing unit generates a first image signal and a first timing control signal. The first and the second conversion units, respectively, converts the first image signal and the first timing control signal into a second image signal and a second timing control signal. The third and the fourth conversion units, respectively, receive and convert the second image signal and the second timing control signal into a third image signal and a third timing control signal. The display unit displays the third image signal according to the third timing control signal.

Abstract: A split-type display system includes a processing device, a display device, and a transmission cable connecting the devices. The processing device includes a processing unit and a low-to-high unit. The processing unit generates a first image signal having both a first transmission rate and a first channel number. The low-to-high unit converts the first image signal into a second image signal having both a second transmission rate and a second channel number. The first transmission rate is lower than the second transmission rate. The display device includes a high-to-low unit and a display unit. The high-to-low unit receives and converts the second image signal into a third image signal having both a third transmission rate and a third channel number. The display unit displays the third image signal. a number of channels of the transmission cable is the same as the second channel number.

Abstract: Disclosed is a graphics processing device including a main SoC, a performance-enhancing SoC, and an external circuit that is set outside any of the two SoCs. The main SoC includes: a first graphics processing unit (GPU) dividing to-be-processed data into a first input part and a second input part, and processing the first output part to generate first output data; and a first transceiver circuit forwarding the second input part to the performance-enhancing SoC via the external circuit, and then receiving second output data via the external circuit and forwarding it. The performance-enhancing SoC includes: a second transceiver circuit receiving the second input part via the external circuit and outputting the second output data to the main SoC via the external circuit; and a second GPU receiving the second input part from the second transceiver circuit and processing this part to provide the second output data for the second transceiver.

Abstract: An image processing device includes a main SoC, an performance-enhancing SoC, and an external circuit set outside any of the two SoCs. The main SoC includes: a data splitter dividing input image data into a first input part and a second input part; a first image processing circuit processing the first input part to generate a first output part; and a transmitter outputting the second input part to the performance-enhancing SoC via the external circuit. The performance-enhancing SoC includes: a receiver receiving the second input part via the external circuit; and a second image processing circuit processing the second input part to generate a second output part. The combination of the two output parts jointly determines a data amount per unit of time which exceeds the processing capability of any of the two image processing circuits. Each of the two SoCs includes a CPU, and the two CPUs cooperate, too.

Abstract: Disclosed is a data processing device including a main SoC, a performance-enhancing SoC, and an external circuit that is set outside any of the two SoCs. The main SoC includes: a first central processing unit (CPU) dividing to-be-processed data into a first input part and a second input part, and processing the first input part to generate first output data; and a first transceiver circuit forwarding the second input part to the performance-enhancing SoC via the external circuit, and then receiving second output data via the external circuit and forwarding it. The performance-enhancing SoC includes: a second transceiver circuit receiving the second input part via the external circuit, and transmitting the second output data to the main SoC via the external circuit; and a second CPU receiving the second input part from the second transceiver circuit and processing it to provide the second output data for the second transceiver circuit.

Abstract: The present invention provides a receiving circuit applied to an HDMI, wherein the receiving circuit includes a decoder, a frame key calculating circuit, a line key calculating circuit and a control circuit. In the operations of the receiving circuit, the decoder decodes a data stream to generate at least one image frame, the frame key calculating circuit is arranged to calculate a frame key according to the image frame, the line key calculating circuit is arranged to calculate a plurality of line keys according to the image frame, and the control circuit determines to turn off or turn on the line key calculating circuit according to whether or not the image frame is displayed on a display panel.