Patents by Inventor Hsu Lee

Hsu Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240332076
    Abstract: Generally, examples are provided relating to conductive features that include a barrier layer, and to methods thereof. In an embodiment, a metal layer is deposited in an opening through a dielectric layer(s) to a source/drain region. The metal layer is along the source/drain region and along a sidewall of the dielectric layer(s) that at least partially defines the opening. The metal layer is nitrided, which includes performing a multiple plasma process that includes at least one directional-dependent plasma process. A portion of the metal layer remains un-nitrided by the multiple plasma process. A silicide region is formed, which includes reacting the un-nitrided portion of the metal layer with a portion of the source/drain region. A conductive material is disposed in the opening on the nitrided portions of the metal layer.
    Type: Application
    Filed: June 10, 2024
    Publication date: October 3, 2024
    Inventors: Wei-Yip Loh, Chih-Wei Chang, Hong-Mao Lee, Chun-Hsien Huang, Yu-Ming Huang, Yan-Ming Tsai, Yu-Shiuan Wang, Hung-Hsu Chen, Yu-Kai Chen, Yu-Wen Cheng
  • Publication number: 20240323677
    Abstract: Techniques are provided for receiving encrypted positioning assistance data, requesting and obtaining cipher keys to decrypt the positioning assistance data. An example method for transmitting a cipher key request includes receiving cipher key information including a start time value, a duration value, and an advance time value, determining an advance time duration that is equal to a sum of the start time value and the duration value minus the advance time value, and transmitting the cipher key request within the advance time duration.
    Type: Application
    Filed: March 21, 2023
    Publication date: September 26, 2024
    Inventors: Kuo-Chun LEE, Arvind Vardarajan SANTHANAM, Shanshan WANG, Liangchi HSU, Abhishek BHATNAGAR, Prashanth MYSORE, Priya RAJAN, Karthik VENKATRAM, Daniel AMERGA, Osama LOTFALLAH, Lenaig Genevieve CHAPONNIERE
  • Publication number: 20240321573
    Abstract: A structure is provided that includes a first conductive component and a first interlayer dielectric (ILD) that surrounds the first conductive component. A self-assembly layer is formed on the first conductive component but not on the first ILD. A first dielectric layer is formed over the first ILD but not over the first conductive component. A second ILD is formed over the first conductive component and over the first ILD. An opening is etched in the second ILD. The opening is at least partially aligned with the first conductive component. The first dielectric layer protects portions of the first ILD located therebelow from being etched. The opening is filled with a conductive material to form a second conductive component in the opening.
    Type: Application
    Filed: May 30, 2024
    Publication date: September 26, 2024
    Inventors: Shao-Kuan LEE, Yung-Hsu WU, Cheng-Chin LEE, Hai-Ching CHEN, Hsin-Yen HUANG, Shau-Lin SHUE
  • Patent number: 12100898
    Abstract: An antenna module includes a feeding end, multiple first forked radiators, and multiple connecting parts. The first forked radiators are disposed side by side. The connecting parts respectively extend from the feeding end to the first forked radiators. The feeding end, the first forked radiators, and the connecting parts are located on a same plane. The antenna module resonates at a frequency band, and a path length from the feeding end to an end of each of the forked radiators through the corresponding connecting part is ΒΌ wavelength of the frequency band.
    Type: Grant
    Filed: September 8, 2022
    Date of Patent: September 24, 2024
    Assignee: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Wu-Hua Chen, I-Shu Lee, Hung-Ming Yu, Chao-Hsu Wu, Yung-Yi Lee, Man-Jung Tsao, Chi-Min Tang, Shao-Chi Wang
  • Patent number: 12081464
    Abstract: Aspects described herein relate to communicating with multiple cells based on two separate subscriptions stored at the UE in a dual subscription dual standby (DSDS) mode, switching to communicate with the multiple cells in a dual subscription dual active (DSDA) mode, transmitting, to at least one of the multiple cells and based on a number of component carriers allowed for a subscription being exceeded by switching to communicate in the DSDA mode, assistance information to indicate a threshold amount of component carriers for the UE, and transmitting, to at least one of the multiple cells and based on the number of component carriers allowed for the subscription being exceeded by switching to communicate in the DSDA mode, a channel quality indicator (CQI) value for one or more cells of the multiple cells to request deactivation of one or more component carriers with, or release of, the one or more cells.
    Type: Grant
    Filed: November 3, 2021
    Date of Patent: September 3, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Kuo-Chun Lee, Arvind Vardarajan Santhanam, Reza Shahidi, Qingxin Chen, Liangchi Hsu, Cheol Hee Park, Mona Agrawal, Hemanth Kumar Rayapati, Sridhar Bandaru
  • Patent number: 12080593
    Abstract: Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a second contact feature over the first contact feature, a barrier layer between the second dielectric layer and the second contact feature, and a liner between the barrier layer and the second contact feature. An interface between the first contact feature and the second contact feature includes the liner but is free of the barrier layer.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: September 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Ping Chen, Ming-Han Lee, Shin-Yi Yang, Yung-Hsu Wu, Chia-Tien Wu, Shau-Lin Shue, Min Cao
  • Publication number: 20240256751
    Abstract: A semiconductor device includes a first cell. The first cell includes a first functional feature, a first sensitivity region, at least one anchor node, wherein each of the at least one anchor node is different from the first functional feature, and a number of anchor nodes of the at least one anchor node linked to the first functional feature is based on a position of the first functional feature relative to the first sensitivity region. The semiconductor device further includes a second cell abutting the first cell. The second cell includes a second functional feature, wherein the second functional feature satisfies a minimum spacing requirement with respect to the first functional feature.
    Type: Application
    Filed: July 19, 2023
    Publication date: August 1, 2024
    Inventors: Nien-Yu TSAI, Chin-Chang HSU, Wen-Ju YANG, Hsien-Hsin Sean LEE
  • Patent number: 12046510
    Abstract: Generally, examples are provided relating to conductive features that include a barrier layer, and to methods thereof. In an embodiment, a metal layer is deposited in an opening through a dielectric layer(s) to a source/drain region. The metal layer is along the source/drain region and along a sidewall of the dielectric layer(s) that at least partially defines the opening. The metal layer is nitrided, which includes performing a multiple plasma process that includes at least one directional-dependent plasma process. A portion of the metal layer remains un-nitrided by the multiple plasma process. A silicide region is formed, which includes reacting the un-nitrided portion of the metal layer with a portion of the source/drain region. A conductive material is disposed in the opening on the nitrided portions of the metal layer.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: July 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yip Loh, Chih-Wei Chang, Hong-Mao Lee, Chun-Hsien Huang, Yu-Ming Huang, Yan-Ming Tsai, Yu-Shiuan Wang, Hung-Hsu Chen, Yu-Kai Chen, Yu-Wen Cheng
  • Patent number: 12040561
    Abstract: An antenna module includes a transceiver chip, a transmitting array antenna, a receiving array antenna, two bandpass filters, and two capacitors. The transmitting array antenna and the receiving array antenna are symmetrically disposed at the two opposite sides of the transceiver chip. One of the bandpass filters is disposed between the transceiver chip and the transmitting array antenna and connected to the transceiver chip and the transmitting array antenna. The other bandpass filter is disposed between the transceiver chip and the receiving array antenna and connected to the transceiver chip and the receiving array antenna. One of the capacitors is disposed between the transmitting array antenna and the corresponding bandpass filter and connected to the transmitting array antenna and the corresponding bandpass filter. The other capacitor is disposed between the receiving array antenna and the corresponding bandpass filter and connected to the receiving array antenna and the corresponding bandpass filter.
    Type: Grant
    Filed: October 17, 2022
    Date of Patent: July 16, 2024
    Assignee: PEGATRON CORPORATION
    Inventors: Tse-Hsuan Wang, Chien-Yi Wu, Chih-Fu Chang, Chao-Hsu Wu, Chih-Yi Chiu, Wei-Han Yen, Tsung-Chi Tsai, Shih-Keng Huang, I-Shu Lee
  • Patent number: 11824553
    Abstract: A unity-gain buffer circuit structure, used to receive an input voltage and output an output voltage, includes a first operational amplifier and a second operational amplifier. The first operational amplifier includes a first positive input, a first output and a first negative input. The second operational amplifier, coupled electrically with the first operational amplifier, includes a second positive input, a second output and a second negative input. The second positive input is used to receive the output voltage. The second output, coupled with first negative input, is used to output a second output voltage. The second negative input, coupled with the second output, is used to receive the second output voltage. After the first negative input receives the second output voltage, an offset voltage between the output voltage outputted from the first operational amplifier and the input voltage received by the first operational amplifier is close to 0.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: November 21, 2023
    Assignee: ADVANCED ANALOG TECHNOLOGY, INC.
    Inventors: Kun-Hsu Lee, Wen Jung Su
  • Publication number: 20230253977
    Abstract: A unity-gain buffer circuit structure, used to receive an input voltage and output an output voltage, includes a first operational amplifier and a second operational amplifier. The first operational amplifier includes a first positive input, a first output and a first negative input. The second operational amplifier, coupled electrically with the first operational amplifier, includes a second positive input, a second output and a second negative input. The second positive input is used to receive the output voltage. The second output, coupled with first negative input, is used to output a second output voltage. The second negative input, coupled with the second output, is used to receive the second output voltage. After the first negative input receives the second output voltage, an offset voltage between the output voltage outputted from the first operational amplifier and the input voltage received by the first operational amplifier is close to 0.
    Type: Application
    Filed: March 30, 2022
    Publication date: August 10, 2023
    Inventors: Kun-Hsu LEE, Wen Jung SU
  • Patent number: 11451216
    Abstract: A power on and power down reset circuit includes a reference voltage generation module, a monitoring voltage generation module, and a voltage comparator. The reference voltage generation module is utilized to generate a reference voltage with a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first resistance, and a second resistance. The monitoring voltage generation module is utilized to generate a monitoring voltage. The voltage comparator is utilized to generate a reset voltage by comparing the reference voltage to the monitoring voltage. Thus, the power on and power down reset circuit can achieve the effect of power savings and decreasing error rate of the reset voltage.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: September 20, 2022
    Assignee: ADVANCED ANALOG TECHNOLOGY, INC.
    Inventor: Kun-Hsu Lee
  • Patent number: 11386562
    Abstract: A computing device generates a user interface that includes a viewing window and a toolbar including a selection tool. The computing device displays a live video depicting one or more individuals in the viewing window of the user interface and generates a segmentation mask for each individual depicted in the live video, where each segmentation mask comprises facial feature vectors of a facial region of each individual. The computing device obtains selection of an individual depicted in the live video and compares facial feature vectors of each of the individuals depicted in the live video with the facial feature vector of the selected individual. The computing device converts the segmentation masks of individuals with corresponding facial feature vectors that do not match the selected facial feature vector to a filter mask and composites the filter mask with a background content of the live video.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: July 12, 2022
    Assignee: CYBERLINK CORP.
    Inventors: Ming-Hung Chiang, Cheng-hsu Lee
  • Patent number: 11351562
    Abstract: A device and method for diffusing volatile substances which obtains the energy required for the autonomous operation thereof from one or more photovoltaic cells. The activation periods and switch-on frequency of the emission means are determined adaptively by an electronic controller depending on the light conditions, thereby maximizing the time in which the device diffuses the volatile substance without compromising its autonomy.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: June 7, 2022
    Inventors: Sergio Luque Vera, Dominic Doyle, Chao Hsu Lee
  • Publication number: 20200211201
    Abstract: A computing device generates a user interface that includes a viewing window and a toolbar including a selection tool. The computing device displays a live video depicting one or more individuals in the viewing window of the user interface and generates a segmentation mask for each individual depicted in the live video, where each segmentation mask comprises facial feature vectors of a facial region of each individual. The computing device obtains selection of an individual depicted in the live video and compares facial feature vectors of each of the individuals depicted in the live video with the facial feature vector of the selected individual. The computing device converts the segmentation masks of individuals with corresponding facial feature vectors that do not match the selected facial feature vector to a filter mask and composites the filter mask with a background content of the live video.
    Type: Application
    Filed: December 3, 2019
    Publication date: July 2, 2020
    Inventors: Ming-Hung Chiang, Cheng-hsu Lee
  • Patent number: 10571995
    Abstract: A power-saving scanning method for a touch device is provided. Firstly, a controller is used to shorten a normal scanning time of a timer into a power-saving scanning time. Then, a counter is used to count the oscillating waveform within the power-saving scanning time to access a power-saving oscillating number. Afterward, the controller is used to convert the power-saving oscillating number into an (L-n)-digit M-bit count value, shift the (L-n)-digit M-bit count value toward the higher digit by n digits, and pad the lower digits with n zeros to form another L-digit M-bit count value so as to generate an M-bit oscillating number simulation value for the determination of touch operation.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: February 25, 2020
    Assignee: ADVANCED ANALOG TECHNOLOGY, INC.
    Inventor: Kun-Hsu Lee
  • Patent number: 10426858
    Abstract: The device for releasing volatile substances comprises a support (9) for positioning a receptacle (3) containing the volatile substances, and means for generating a flow of air for releasing the volatile substances, and which is characterized in that said means for generating a flow of air comprise a mobile body (1) joined to said support (9), at least one magnet (2) disposed in said mobile body (1), and means for generating a magnetic flux (4, 5), the operation of which causes the movement of said mobile body (1) by means of the repulsive force between the at least one magnet (2) in the mobile body (1) and the magnetic flux. An improvement in the energy consumption is permitted, using a low-consumption periodic operation, aided by magnetic means.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: October 1, 2019
    Assignee: Zobele Espana, S.A.
    Inventors: Sergio Luque Vera, Dominic Doyle, Chao Hsu Lee
  • Patent number: 10426859
    Abstract: A device for releasing volatile substances comprising a container containing the volatile substances located in a fixed position, and means for generating an air flow in order to release the volatile substances, the means for generating an air flow comprising a movable body, the movement of which generates the air flow; at least one magnet arranged on said movable body; and means for generating magnetic flux, the actuation of which causes the displacement of the movable body by means of the repulsion force between said at least one magnet in the movable body and the magnetic flux. The device enables energy consumption to be improved by using magnetically assisted periodic low-consumption actuation.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: October 1, 2019
    Assignee: ZOBELE ESPA{grave over (N)}A, S.A.
    Inventors: Sergio Luque Vera, Dominic Doyle, Chao Hsu Lee
  • Patent number: 10234993
    Abstract: A touch system includes a circuit board, touch pads, a control chip and an insulation board. The circuit board has a conductive board body including configuration regions. The touch pads is spaced from the configuration regions by the conductive board body. Each touch pad includes at least one touch portion. The control chip includes a multiplex module coupling the touch pads and an oscillation control module coupling the conductive board body. The oscillation control module conducts alternately the multiplex module and every touch portions to utilize a work voltage for generating a voltage oscillation wave respective to each conducted touch portion. The voltage oscillation wave is transmitted to the conductive board body. When an ion-contained liquid is on the insulation board by covering partly the conductive board body and the touch portion, a capacitance effect therebetween is forming by the work voltage, but further erased by the voltage oscillation wave.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: March 19, 2019
    Assignee: ADVANCED ANALOG TECHNOLOGY, INC.
    Inventor: Kun-Hsu Lee
  • Publication number: 20190009294
    Abstract: A device and method for diffusing volatile substances which obtains the energy required for the autonomous operation thereof from one or more photovoltaic cells. The activation periods and switch-on frequency of the emission means are determined adaptively by an electronic controller depending on the light conditions, thereby maximizing the time in which the device diffuses the volatile substance without compromising its autonomy.
    Type: Application
    Filed: December 19, 2016
    Publication date: January 10, 2019
    Inventors: Sergio LUQUE VERA, Dominic DOYLE, Chao, Hsu LEE