Patents by Inventor Hsu-Lun Liu
Hsu-Lun Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240047403Abstract: A semiconductor package structure includes a conductive pad formed over a substrate. The semiconductor package structure also includes a passivation layer formed over the conductive pad. The semiconductor package structure further includes a first via structure formed through the passivation layer and in contact with the conductive pad. The semiconductor package structure also includes a first encapsulating material surrounding the first via structure. The semiconductor package structure further includes a redistribution layer structure formed over the first via structure. The first via structure has a lateral extending portion embedded in the first encapsulating material near a top surface of the first via structure, and the lateral extending portion has a width increasing in a direction toward the redistribution layer structure.Type: ApplicationFiled: October 11, 2023Publication date: February 8, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Neng-Chieh CHANG, Po-Hao TSAI, Ming-Da CHENG, Wen-Hsiung LU, Hsu-Lun LIU
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Publication number: 20240021499Abstract: Some devices included a substrate; and a through via, including a plurality of scallops adjacent the through via in a first region and a plurality of scallops adjacent the through via in a second region, the of scallops having a first depth, the scallops having a greater depth. Some devices include an opening extending into a substrate, including a first region and a second region. Sidewalls of the opening include a stack of first concave portions extending a first distance into the first substrate, and a stack of second concave portions extending a second distance, greater than and parallel to the first distance, into the first substrate. A conductor partially fills the first concave portions and at least partially fills the respective second concave portions.Type: ApplicationFiled: July 31, 2023Publication date: January 18, 2024Inventors: Hsu-Lun Liu, Wen-Hsiung Lu, Ming-Da Cheng, Chen-En Yen, Cheng-Lung Yang, Kuanchih Huang
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Patent number: 11817413Abstract: A semiconductor package structure includes a conductive pad formed over a substrate. The structure also includes a passivation layer formed over the conductive pad. The structure also includes a first via structure formed through the passivation layer and in contact with the conductive pad. The structure also includes a first encapsulating material surrounding the first via structure. The structure also includes a redistribution layer structure formed over the first via structure. The first via structure has a lateral extending portion embedded in the first encapsulating material near a top surface of the first via structure.Type: GrantFiled: August 30, 2021Date of Patent: November 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Neng-Chieh Chang, Po-Hao Tsai, Ming-Da Cheng, Wen-Hsiung Lu, Hsu-Lun Liu
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Patent number: 11776881Abstract: A through via comprising sidewalls having first scallops in a first region and second scallops in a second region and a method of forming the same are disclosed. In an embodiment, a semiconductor device includes a first substrate; and a through via extending through the substrate, the substrate including a first plurality of scallops adjacent the through via in a first region of the substrate and a second plurality of scallops adjacent the through via in a second region of the substrate, each of the scallops of the first plurality of scallops having a first depth, each of the scallops of the second plurality of scallops having a second depth, the first depth being greater than the second depth.Type: GrantFiled: March 25, 2022Date of Patent: October 3, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsu-Lun Liu, Wen-Hsiung Lu, Ming-Da Cheng, Chen-En Yen, Cheng-Lung Yang, Kuanchih Huang
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Publication number: 20230154880Abstract: A method includes forming a seed layer over a first conductive feature of a wafer, forming a patterned plating mask on the seed layer, and plating a second conductive feature in an opening in the patterned plating mask. The plating includes performing a plurality of plating cycles, with each of the plurality of plating cycles including a first plating process performed using a first plating current density, and a second plating process performed using a second plating current density lower than the first plating current density. The patterned plating mask is then removed, and the seed layer is etched.Type: ApplicationFiled: January 6, 2023Publication date: May 18, 2023Inventors: Po-Hao Tsai, Ming-Da Cheng, Wen-Hsiung Lu, Hsu-Lun Liu, Kai-Di Wu, Su-Fei Lin
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Publication number: 20230067826Abstract: A semiconductor package structure includes a conductive pad formed over a substrate. The structure also includes a passivation layer formed over the conductive pad. The structure also includes a first via structure formed through the passivation layer and in contact with the conductive pad. The structure also includes a first encapsulating material surrounding the first via structure. The structure also includes a redistribution layer structure formed over the first via structure. The first via structure has a lateral extending portion embedded in the first encapsulating material near a top surface of the first via structure.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Neng-Chieh CHANG, Po-Hao TSAI, Ming-Da CHENG, Wen-Hsiung LU, Hsu-Lun LIU
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Patent number: 11594508Abstract: A method includes forming a seed layer over a first conductive feature of a wafer, forming a patterned plating mask on the seed layer, and plating a second conductive feature in an opening in the patterned plating mask. The plating includes performing a plurality of plating cycles, with each of the plurality of plating cycles including a first plating process performed using a first plating current density, and a second plating process performed using a second plating current density lower than the first plating current density. The patterned plating mask is then removed, and the seed layer is etched.Type: GrantFiled: October 13, 2020Date of Patent: February 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Po-Hao Tsai, Ming-Da Cheng, Wen-Hsiung Lu, Hsu-Lun Liu, Kai-Di Wu, Su-Fei Lin
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Publication number: 20220351983Abstract: In a method of manufacturing a semiconductor device first conductive layers are formed over a substrate. A first photoresist layer is formed over the first conductive layers. The first conductive layers are etched by using the first photoresist layer as an etching mask, to form an island pattern of the first conductive layers separated from a bus bar pattern of the first conductive layers by a ring shape groove. A connection pattern is formed to connect the island pattern and the bus bar pattern. A second photoresist layer is formed over the first conductive layers and the connection pattern. The second photoresist layer includes an opening over the island pattern. Second conductive layers are formed on the island pattern in the opening. The second photoresist layer is removed, and the connection pattern is removed, thereby forming a bump structure.Type: ApplicationFiled: July 14, 2022Publication date: November 3, 2022Inventors: Wen-Hsiung LU, Ming-Da CHENG, Su-Fei LIN, Hsu-Lun LIU, Chien-Pin CHAN, Yung-Sheng LIN
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Patent number: 11417539Abstract: In a method of manufacturing a semiconductor device first conductive layers are formed over a substrate. A first photoresist layer is formed over the first conductive layers. The first conductive layers are etched by using the first photoresist layer as an etching mask, to form an island pattern of the first conductive layers separated from a bus bar pattern of the first conductive layers by a ring shape groove. A connection pattern is formed to connect the island pattern and the bus bar pattern. A second photoresist layer is formed over the first conductive layers and the connection pattern. The second photoresist layer includes an opening over the island pattern. Second conductive layers are formed on the island pattern in the opening. The second photoresist layer is removed, and the connection pattern is removed, thereby forming a bump structure.Type: GrantFiled: October 30, 2020Date of Patent: August 16, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Hsiung Lu, Ming-Da Cheng, Su-Fei Lin, Hsu-Lun Liu, Chien-Pin Chan, Yung-Sheng Lin
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Publication number: 20220216133Abstract: A through via comprising sidewalls having first scallops in a first region and second scallops in a second region and a method of forming the same are disclosed. In an embodiment, a semiconductor device includes a first substrate; and a through via extending through the substrate, the substrate including a first plurality of scallops adjacent the through via in a first region of the substrate and a second plurality of scallops adjacent the through via in a second region of the substrate, each of the scallops of the first plurality of scallops having a first depth, each of the scallops of the second plurality of scallops having a second depth, the first depth being greater than the second depth.Type: ApplicationFiled: March 25, 2022Publication date: July 7, 2022Inventors: Hsu-Lun Liu, Wen-Hsiung Lu, Ming-Da Cheng, Chen-En Yen, Cheng-Lung Yang, Kuanchih Huang
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Patent number: 11289404Abstract: A through via comprising sidewalls having first scallops in a first region and second scallops in a second region and a method of forming the same are disclosed. In an embodiment, a semiconductor device includes a first substrate; and a through via extending through the substrate, the substrate including a first plurality of scallops adjacent the through via in a first region of the substrate and a second plurality of scallops adjacent the through via in a second region of the substrate, each of the scallops of the first plurality of scallops having a first depth, each of the scallops of the second plurality of scallops having a second depth, the first depth being greater than the second depth.Type: GrantFiled: January 17, 2020Date of Patent: March 29, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsu-Lun Liu, Wen-Hsiung Lu, Ming-Da Cheng, Chen-En Yen, Cheng-Lung Yang, Kuanchih Huang
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Publication number: 20210375815Abstract: A method includes forming a seed layer over a first conductive feature of a wafer, forming a patterned plating mask on the seed layer, and plating a second conductive feature in an opening in the patterned plating mask. The plating includes performing a plurality of plating cycles, with each of the plurality of plating cycles including a first plating process performed using a first plating current density, and a second plating process performed using a second plating current density lower than the first plating current density. The patterned plating mask is then removed, and the seed layer is etched.Type: ApplicationFiled: October 13, 2020Publication date: December 2, 2021Inventors: Po-Hao Tsai, Ming-Da Cheng, Wen-Hsiung Lu, Hsu-Lun Liu, Kai-Di Wu, Su-Fei Lin
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Patent number: 11177137Abstract: A method includes bonding a first surface of a first semiconductor substrate to a first surface of a second semiconductor substrate and forming a cavity in the first area of the first semiconductor substrate, where forming the cavity comprises: supplying a passivation gas mixture that deposits a passivation layer on a bottom surface and sidewalls of the cavity, where during deposition of the passivation layer, a deposition rate of the passivation layer on the bottom surface of the cavity is the same as a deposition rate of the passivation layer on sidewalls of the cavity; and etching the first area of the first semiconductor substrate using an etching gas, where the etching gas is supplied concurrently with the passivation gas mixture, etching the first area of the first semiconductor substrate comprises etching in a vertical direction at a greater rate than etching in a lateral direction.Type: GrantFiled: January 17, 2020Date of Patent: November 16, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Hsiung Lu, Hui-Min Huang, Ming-Da Cheng, Wei-Hung Lin, Chen-En Yen, Hsu-Lun Liu
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Publication number: 20210272819Abstract: In a method of manufacturing a semiconductor device first conductive layers are formed over a substrate. A first photoresist layer is formed over the first conductive layers. The first conductive layers are etched by using the first photoresist layer as an etching mask, to form an island pattern of the first conductive layers separated from a bus bar pattern of the first conductive layers by a ring shape groove. A connection pattern is formed to connect the island pattern and the bus bar pattern. A second photoresist layer is formed over the first conductive layers and the connection pattern. The second photoresist layer includes an opening over the island pattern. Second conductive layers are formed on the island pattern in the opening. The second photoresist layer is removed, and the connection pattern is removed, thereby forming a bump structure.Type: ApplicationFiled: October 30, 2020Publication date: September 2, 2021Inventors: Wen-Hsiung LU, Ming-Da CHENG, Su-Fei LIN, Hsu-Lun LIU, Chien-Pin CHAN, Yung-Sheng LIN
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Publication number: 20210225735Abstract: A through via comprising sidewalls having first scallops in a first region and second scallops in a second region and a method of forming the same are disclosed. In an embodiment, a semiconductor device includes a first substrate; and a through via extending through the substrate, the substrate including a first plurality of scallops adjacent the through via in a first region of the substrate and a second plurality of scallops adjacent the through via in a second region of the substrate, each of the scallops of the first plurality of scallops having a first depth, each of the scallops of the second plurality of scallops having a second depth, the first depth being greater than the second depth.Type: ApplicationFiled: January 17, 2020Publication date: July 22, 2021Inventors: Hsu-Lun Liu, Wen-Hsiung Lu, Ming-Da Cheng, Chen-En Yen, Cheng-Lung Yang, Kuanchih Huang
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Publication number: 20210225658Abstract: A method includes bonding a first surface of a first semiconductor substrate to a first surface of a second semiconductor substrate and forming a cavity in the first area of the first semiconductor substrate, where forming the cavity comprises: supplying a passivation gas mixture that deposits a passivation layer on a bottom surface and sidewalls of the cavity, where during deposition of the passivation layer, a deposition rate of the passivation layer on the bottom surface of the cavity is the same as a deposition rate of the passivation layer on sidewalls of the cavity; and etching the first area of the first semiconductor substrate using an etching gas, where the etching gas is supplied concurrently with the passivation gas mixture, etching the first area of the first semiconductor substrate comprises etching in a vertical direction at a greater rate than etching in a lateral direction.Type: ApplicationFiled: January 17, 2020Publication date: July 22, 2021Inventors: Wen-Hsiung Lu, Hui-Min Huang, Ming-Da Cheng, Wei-Hung Lin, Chen-En Yen, Hsu-Lun Liu