Abstract: Some implementations described herein provide techniques and semiconductor devices in which a dielectric region is included in a nanostructure transistor. The dielectric region, which may correspond to an air gap, may be located between dielectric spacer layers located along a sidewall of a metal gate structure. Techniques to form the dielectric region may include using a temporary spacer layer between the dielectric spacer layers during manufacturing of the nanostructure transistor. The temporary spacer layer may include a silicon germanium material having a reaction mechanism that allows the temporary spacer layer to be selectively removed without causing damage to the dielectric spacer layers, the metal gate structure, or other portions of the nanostructure transistor.

Abstract: Recesses may be formed in portions of an ILD layer of a semiconductor device in a highly uniform manner. Uniformity in depths of the recesses may be increased by configuring flows of gases in an etch tool to promote uniformity of etch rates (and thus, etch depth) across the semiconductor device, from semiconductor device to semiconductor device, and/or from wafer to wafer. In particular, the flow rates of gases at various inlets of the etch tool may be optimized to provide recess depth tuning, which increases the process window for forming the recesses in the portions of the ILD layer. In this way, the increased uniformity of the recesses in the portions of the ILD layer enables highly uniform capping layers to be formed in the recesses.

Abstract: A method, for making a semiconductor device, includes forming a first fin over a substrate. The method includes forming a dummy gate stack on the first fin. The method includes forming a first gate spacer along a side of the dummy gate stack. The first gate spacer includes a first dielectric material. The method includes forming a second gate spacer along a side of the first gate spacer. The second gate spacer includes a semiconductor material. The method includes forming a source/drain region in the first fin adjacent the second gate spacer. The method includes removing at least a portion of the second gate spacer to form a void extending between the first gate spacer and the source/drain region.

Abstract: Spacer layers on sidewalls of a dummy gate structure included in a semiconductor device are trimmed or etched prior to or during a replacement gate process in which the dummy gate structure is replaced with a replacement gate structure. A radical surface treatment operation is performed to etch the spacer layers, which is a type of plasma treatment in which radicals are generated using a plasma. The radicals in the plasma are used to etch the spacer layers such that the shape and/or the geometry of the remaining portions of the spacer layers reduces, minimizes, and/or prevents the likelihood of an antenna defect being formed in the spacer layers and/or in a work function metal layer of the replacement gate structure. This reduces, minimizes, and/or prevents the likelihood of occurrence of damage and/or defects in the replacement gate structure in subsequent processing operations for the semiconductor device.

Abstract: A method, for making a semiconductor device, includes forming a first fin over a substrate. The method includes forming a dummy gate stack on the first fin. The method includes forming a first gate spacer along a side of the dummy gate stack. The first gate spacer includes a first dielectric material. The method includes forming a second gate spacer along a side of the first gate spacer. The second gate spacer includes a semiconductor material. The method includes forming a source/drain region in the first fin adjacent the second gate spacer. The method includes removing at least a portion of the second gate spacer to form a void extending between the first gate spacer and the source/drain region.

Abstract: In a method of manufacturing a semiconductor device, a sacrificial gate structure including sacrificial gate electrode is formed over a substrate. A first dielectric layer is formed over the sacrificial gate structure. A second dielectric layer is formed over the first dielectric layer. The second and first dielectric layers are planarized and recessed, and an upper portion of the sacrificial gate structure is exposed. A third dielectric layer is formed over the exposed sacrificial gate structure and over the first dielectric layer. A fourth dielectric layer is formed over the third dielectric layer. The fourth and third dielectric layers are planarized, and the sacrificial gate electrode is exposed and part of the third dielectric layer remains on the recessed first dielectric layer. The recessing the first dielectric layer comprises a first etching operation and a second etching operation using a different etching as from the first etching operation.

Abstract: A method, for making a semiconductor device, includes forming a first fin over a substrate. The method includes forming a dummy gate stack on the first fin. The method includes forming a first gate spacer along a side of the dummy gate stack. The first gate spacer includes a first dielectric material. The method includes forming a second gate spacer along a side of the first gate spacer. The second gate spacer includes a semiconductor material. The method includes forming a source/drain region in the first fin adjacent the second gate spacer. The method includes removing at least a portion of the second gate spacer to form a void extending between the first gate spacer and the source/drain region.