Patents by Inventor Hsu Shun Chen
Hsu Shun Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220336016Abstract: A memory circuit includes a bias voltage generator including a bias voltage node, an activation voltage generator including a resistive device, and a first amplifier, a drive circuit including a second amplifier including an input terminal coupled to the bias voltage node, and a resistive random-access memory (RRAM) array. The activation voltage generator and the first amplifier are configured to generate a portion of a bias voltage level on the bias voltage node based on a resistance of the resistive device, and the drive circuit is configured to output a drive voltage having the bias voltage level to the RRAM array.Type: ApplicationFiled: July 1, 2022Publication date: October 20, 2022Inventors: Chung-Cheng CHOU, Hsu-Shun CHEN, Chien-An LAI, Pei-Ling TSENG, Zheng-Jun LIN
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Patent number: 11393528Abstract: A memory circuit includes a bias voltage generator, a drive circuit, and a resistive random-access memory (RRAM) device. The bias voltage generator includes a first transistor configured to generate a voltage difference based on a first current and an activation voltage, and is configured to output the activation voltage and a bias voltage based on the voltage difference. The drive circuit is configured to receive the bias voltage and output a drive voltage having a voltage level based on the bias voltage, and the RRAM device is configured to receive the activation voltage and conduct a second current responsive to the drive voltage and the activation voltage.Type: GrantFiled: February 18, 2021Date of Patent: July 19, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Cheng Chou, Chien-An Lai, Hsu-Shun Chen, Zheng-Jun Lin, Pei-Ling Tseng
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Publication number: 20210174871Abstract: A memory circuit includes a bias voltage generator, a drive circuit, and a resistive random-access memory (RRAM) device. The bias voltage generator includes a first transistor configured to generate a voltage difference based on a first current and an activation voltage, and is configured to output the activation voltage and a bias voltage based on the voltage difference. The drive circuit is configured to receive the bias voltage and output a drive voltage having a voltage level based on the bias voltage, and the RRAM device is configured to receive the activation voltage and conduct a second current responsive to the drive voltage and the activation voltage.Type: ApplicationFiled: February 18, 2021Publication date: June 10, 2021Inventors: Chung-Cheng CHOU, Chien-An LAI, Hsu-Shun CHEN, Zheng-Jun LIN, Pei-Ling TSENG
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Patent number: 10930344Abstract: A memory circuit includes a bias voltage generator, a drive circuit, and a resistive random-access memory (RRAM) device. The bias voltage generator includes a first current path configured to receive a first current from a current source, and output a bias voltage based on a voltage difference generated from conduction of the first current in the first current path. The drive circuit is configured to receive the bias voltage and output a drive voltage having a voltage level based on the bias voltage, and the RRAM device is configured to conduct a second current responsive to the drive voltage.Type: GrantFiled: May 24, 2019Date of Patent: February 23, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chung-Cheng Chou, Hsu-Shun Chen, Chien-An Lai, Pei-Ling Tseng, Zheng-Jun Lin
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Publication number: 20190371398Abstract: A memory circuit includes a bias voltage generator, a drive circuit, and a resistive random-access memory (RRAM) device. The bias voltage generator includes a first current path configured to receive a first current from a current source, and output a bias voltage based on a voltage difference generated from conduction of the first current in the first current path. The drive circuit is configured to receive the bias voltage and output a drive voltage having a voltage level based on the bias voltage, and the RRAM device is configured to conduct a second current responsive to the drive voltage.Type: ApplicationFiled: May 24, 2019Publication date: December 5, 2019Inventors: Chung-Cheng CHOU, Hsu-Shun CHEN, Chien-An LAI, Pei-Ling TSENG, Zheng-Jun LIN
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Patent number: 9934864Abstract: A nonvolatile memory device comprises a cell array including a memory cell. The nonvolatile memory device also includes a reference signal generator configured to generate a reference current for reading data stored in the memory cell. The reference signal generator includes a first circuit coupled to a current summation node and having a reference cell. The first circuit is configured to generate a first current that flows between drain and source terminals of a transistor in the reference cell. The reference signal generator also includes a second circuit coupled to the current summation node and configured to generate a second current that is a temperature-dependent current. The current summation node is configured to combine the first and second currents to generate the reference current that tracks a temperature trend of a current flowing through the memory cell.Type: GrantFiled: February 2, 2017Date of Patent: April 3, 2018Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Hsu-Shun Chen, Gu-Huan Li, Cheng-Hsiung Kuo, Yue-Der Chih
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Publication number: 20170148523Abstract: A nonvolatile memory device comprises a cell array including a memory cell. The nonvolatile memory device also includes a reference signal generator configured to generate a reference current for reading data stored in the memory cell. The reference signal generator includes a first circuit coupled to a current summation node and having a reference cell. The first circuit is configured to generate a first current that flows between drain and source terminals of a transistor in the reference cell. The reference signal generator also includes a second circuit coupled to the current summation node and configured to generate a second current that is a temperature-dependent current. The current summation node is configured to combine the first and second currents to generate the reference current that tracks a temperature trend of a current flowing through the memory cell.Type: ApplicationFiled: February 2, 2017Publication date: May 25, 2017Inventors: Hsu-Shun Chen, Gu-Huan Li, Cheng-Hsiung Kuo, Yue-Der Chih
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Patent number: 9613710Abstract: A multiple-time programmable (MTP) structure is provided that can operate using a power supply with a supply voltage of 1.5 V to 5.5 V. When the supply voltage is above a first voltage, a first circuit is configured to induce a second constant voltage at a drain of a second transistor, and to induce the second constant voltage on a terminal in a third circuit. In some embodiments, the third circuit provides a third constant voltage on a gate of a third transistor. When the supply voltage is below the first voltage, a fifth circuit is configured to induce a fourth constant voltage on a terminal in the third circuit. The fourth constant voltage is substantially equal to the second constant voltage.Type: GrantFiled: October 20, 2016Date of Patent: April 4, 2017Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Hsu-Shun Chen, Cheng-Hsiung Kuo, Gu-Huan Li, Chung-Chieh Chen, Yu-Der Chih
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Patent number: 9595340Abstract: A nonvolatile memory device comprises a cell array including a memory cell. The nonvolatile memory device also includes a reference signal generator configured to generate a reference current for reading data stored in the memory cell. The reference signal generator includes a first circuit coupled to a current summation node and having a reference cell. The first circuit is configured to generate a first current that flows between drain and source terminals of a transistor in the reference cell. The reference signal generator also includes a second circuit coupled to the current summation node and configured to generate a second current that is a temperature-dependent current. The current summation node is configured to combine the first and second currents to generate the reference current that tracks a temperature trend of a current flowing through the memory cell.Type: GrantFiled: January 20, 2015Date of Patent: March 14, 2017Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Hsu-Shun Chen, Gu-Huan Li, Cheng-Hsiung Kuo, Yue-Der Chih
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Publication number: 20170040063Abstract: A multiple-time programmable (MTP) structure is provided that can operate using a power supply with a supply voltage of 1.5 V to 5.5 V. When the supply voltage is above a first voltage, a first circuit is configured to induce a second constant voltage at a drain of a second transistor, and to induce the second constant voltage on a terminal in a third circuit. In some embodiments, the third circuit provides a third constant voltage on a gate of a third transistor. When the supply voltage is below the first voltage, a fifth circuit is configured to induce a fourth constant voltage on a terminal in the third circuit. The fourth constant voltage is substantially equal to the second constant voltage.Type: ApplicationFiled: October 20, 2016Publication date: February 9, 2017Inventors: Hsu-Shun Chen, Cheng-Hsiung Kuo, Gu-Huan Li, Chung-Chieh Chen, Yu-Der Chih
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Patent number: 9478297Abstract: A multiple-time programmable (MTP) structure is provided that can operate using a power supply with a supply voltage of 1.5 V to 5.5 V. When the supply voltage is above a first voltage, a first circuit is configured to induce a second constant voltage at a drain of a second transistor, and to induce the second constant voltage on a terminal in a third circuit. In some embodiments, the third circuit provides a third constant voltage on a gate of a third transistor. When the supply voltage is below the first voltage, a fifth circuit is configured to induce a fourth constant voltage on a terminal in the third circuit. The fourth constant voltage is substantially equal to the second constant voltage.Type: GrantFiled: January 31, 2014Date of Patent: October 25, 2016Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Hsu-Shun Chen, Cheng-Hsiung Kuo, Gu-Huan Li, Chung-Chieh Chen, Yue-Der Chih
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Publication number: 20160211030Abstract: A nonvolatile memory device comprises a cell array including a memory cell. The nonvolatile memory device also includes a reference signal generator configured to generate a reference current for reading data stored in the memory cell. The reference signal generator includes a first circuit coupled to a current summation node and having a reference cell. The first circuit is configured to generate a first current that flows between drain and source terminals of a transistor in the reference cell. The reference signal generator also includes a second circuit coupled to the current summation node and configured to generate a second current that is a temperature-dependent current. The current summation node is configured to combine the first and second currents to generate the reference current that tracks a temperature trend of a current flowing through the memory cell.Type: ApplicationFiled: January 20, 2015Publication date: July 21, 2016Inventors: HSU-SHUN CHEN, GU-HUAN LI, CHENG-HSIUNG KUO, YUE-DER CHIH
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Patent number: 9324383Abstract: An integrated circuit that includes a generator unit connected to one or more pull-up units, one or more pull-up units connected to one or more source lines and an array of memory cells connected to the one or more source lines. The generator unit is configured to set a first voltage signal of each pull-up unit of the one or more pull-up units. Each pull-up unit of the one or more pull-up units is connected with the corresponding source line of the one or more source lines and is configured to set a current of the corresponding source line of the one or more source lines. The array of memory cells is electrically connected to the one or more source lines and one or more bit lines.Type: GrantFiled: March 20, 2014Date of Patent: April 26, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Gu-Huan Li, Hsu-Shun Chen, Chung-Chieh Chen, Cheng-Hsiung Kuo
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Patent number: 9190995Abstract: An electronic device includes a first circuit, a second circuit, and a power on control (POC) circuit. The POC circuit includes an enable terminal electrically connected to a first output of the first circuit, a first input terminal electrically connected to a first voltage supply, a second input terminal electrically connected to a second voltage supply, and an output terminal. The second circuit includes a biasing-sensitive circuit, and a logic circuit including a first input terminal electrically connected to a second output of the first circuit, a second input terminal electrically connected to the output of the POC circuit, and an output terminal electrically connected to an enable terminal of the biasing-sensitive circuit.Type: GrantFiled: November 19, 2014Date of Patent: November 17, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jerry Chen, Hsu-Shun Chen, Gu-Huan Li, Cheng-Hsiung Kuo, Yue-Der Chih
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Publication number: 20150269974Abstract: An integrated circuit that includes a generator unit connected to one or more pull-up units, one or more pull-up units connected to one or more source lines and an array of memory cells connected to the one or more source lines. The generator unit is configured to set a first voltage signal of each pull-up unit of the one or more pull-up units. Each pull-up unit of the one or more pull-up units is connected with the corresponding source line of the one or more source lines and is configured to set a current of the corresponding source line of the one or more source lines. The array of memory cells is electrically connected to the one or more source lines and one or more bit lines.Type: ApplicationFiled: March 20, 2014Publication date: September 24, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Gu-Huan LI, Hsu-Shun CHEN, Chung-Chieh CHEN, Cheng-Hsiung KUO
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Publication number: 20150221383Abstract: A multiple-time programmable (MTP) structure is provided that can operate using a power supply with a supply voltage of 1.5 V to 5.5 V. When the supply voltage is above a first voltage, a first circuit is configured to induce a second constant voltage at a drain of a second transistor, and to induce the second constant voltage on a terminal in a third circuit. In some embodiments, the third circuit provides a third constant voltage on a gate of a third transistor. When the supply voltage is below the first voltage, a fifth circuit is configured to induce a fourth constant voltage on a terminal in the third circuit. The fourth constant voltage is substantially equal to the second constant voltage.Type: ApplicationFiled: January 31, 2014Publication date: August 6, 2015Inventors: Hsu-Shun Chen, Cheng-Hsiung Kuo, Gu-Huan Li, Chung-Chieh Chen, Yue-Der Chih
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Patent number: 9099168Abstract: An integrated circuit includes a positive power supply node, a current tracking circuit, and a current mirroring circuit including a plurality of current paths coupled in parallel. The currents of the plurality of current paths mirror a current of the current tracking circuit. The current mirroring circuit is configured to turn off the plurality of current paths one-by-one in response to a reduction in a positive power supply voltage on the positive power supply node. The integrated circuit further includes a charging node receiving a summation current of the plurality of current paths, wherein a voltage on the charging node is configured to increase through a charging of the summation current.Type: GrantFiled: September 14, 2012Date of Patent: August 4, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsu-Shun Chen, Cheng-Hung Lee, Hong-Chen Cheng, Chung-Yi Wu
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Publication number: 20150070057Abstract: An electronic device includes a first circuit, a second circuit, and a power on control (POC) circuit. The POC circuit includes an enable terminal electrically connected to a first output of the first circuit, a first input terminal electrically connected to a first voltage supply, a second input terminal electrically connected to a second voltage supply, and an output terminal. The second circuit includes a biasing-sensitive circuit, and a logic circuit including a first input terminal electrically connected to a second output of the first circuit, a second input terminal electrically connected to the output of the POC circuit, and an output terminal electrically connected to an enable terminal of the biasing-sensitive circuit.Type: ApplicationFiled: November 19, 2014Publication date: March 12, 2015Inventors: Jerry Chen, Hsu-Shun Chen, Gu-Huan Li, Cheng-Hsiung Kuo, Yue-Der Chih
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Patent number: 8928372Abstract: An electronic device includes a first circuit, a second circuit, and a power on control (POC) circuit. The POC circuit includes an enable terminal electrically connected to a first output of the first circuit, a first input terminal electrically connected to a first voltage supply, a second input terminal electrically connected to a second voltage supply, and an output terminal. The second circuit includes a biasing-sensitive circuit, and a logic circuit including a first input terminal electrically connected to a second output of the first circuit, a second input terminal electrically connected to the output of the POC circuit, and an output terminal electrically connected to an enable terminal of the biasing-sensitive circuit.Type: GrantFiled: March 8, 2013Date of Patent: January 6, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jerry Chen, Hsu-Shun Chen, Gu-Huan Li, Cheng-Hsiung Kuo, Yue-Der Chih
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Patent number: 8634268Abstract: The present application discloses a memory circuit having a first decoder coupled to a first memory bank and configured to receive a plurality of address control signals and to generate a first plurality of cell selection signals responsive to the plurality of address control signals and a second decoder coupled to a second memory bank and configured to receive a plurality of inverted address control signals and to generate a second plurality of cell selection signals responsive to the plurality of inverted address control signals. The memory circuit also has an address control signal buffer coupled to the second decoder and configured to convert the plurality of address control signals into the plurality of inverted address control signals.Type: GrantFiled: October 27, 2010Date of Patent: January 21, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng Hung Lee, Hsu-Shun Chen