Patents by Inventor Hsu-Tien Hu

Hsu-Tien Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140238653
    Abstract: A heat sink using porous graphite having graphite particle-stacked porous graphite is provided. The heat sink may provide good heat conductivity and improve strength of carbon foam.
    Type: Application
    Filed: May 2, 2014
    Publication date: August 28, 2014
    Applicant: SHUOEN TECH. CO., LTD
    Inventors: Hsu-Tien HU, Jiun-Hsu HSIAO
  • Patent number: 8753552
    Abstract: A heat sink using porous graphite having graphite particle-stacked porous graphite is provided. The heat sink may provide good heat conductivity and improve strength of carbon foam. Also, a manufacturing method of porous graphite is provided.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: June 17, 2014
    Assignee: Shuoen Tech. Co., Ltd
    Inventors: Hsu-Tien Hu, Jiun-Hsu Hsiao
  • Publication number: 20130277035
    Abstract: A manufacturing method of carbonaceous heat sink includes a mixing step and a molding step. In the mixing step, a graphite material is mixed with a thermosetting binder to obtain a mixture. In the molding step, the mixture is pressure formed with a mold into the carbonaceous heat sink, Preferably, the carbonaceous heat sink can increase its carbonaceous percentage by using a heat treating step. The manufacturing method can produce carbonaceous heat sinks with a high carbonaceous percentage with a low cost.
    Type: Application
    Filed: April 18, 2013
    Publication date: October 24, 2013
    Applicant: Shuoen Tech. Co., Ltd.
    Inventors: Hsu-Tien Hu, Pi-Min Lin, Chao-Yin Chuang
  • Publication number: 20120211212
    Abstract: A heat sink using porous graphite having graphite particle-stacked porous graphite is provided. The heat sink may provide good heat conductivity and improve strength of carbon foam. Also, a manufacturing method of porous graphite is provided.
    Type: Application
    Filed: June 7, 2011
    Publication date: August 23, 2012
    Applicant: SHUOEN TECH CO., LTD.
    Inventors: Hsu-Tien HU, Jiun-Hsu Hsiao
  • Patent number: 6440836
    Abstract: The present invention discloses a dual-photoresist method for forming fine-pitched solder bumps on flip chips by utilizing two separate layers of photoresist, i.e., a first thin photoresist layer for patterning the BLM layers on top of the aluminum bonding pads and a second thick photoresist layer for patterning the via openings on top of the BLM layers to supply the necessary thickness required for the solder bumps. The first, thin photoresist layer permits an accurate imaging process to be conducted without focusing problems which are normally associated with thick photoresist layers. As an optional step, the present invention may further utilize a thin layer of non-leachable metal such as Cu or Ni for coating on top of the BLM layer and thus further improving the electrical characteristics of the solder bumps subsequently formed thereon.
    Type: Grant
    Filed: March 16, 1999
    Date of Patent: August 27, 2002
    Assignee: Industrial Technology Research Institute
    Inventors: Szu-Wei Lu, Ling-Chen Kung, Ruoh-Huey Uang, Hsu-Tien Hu
  • Patent number: 6358836
    Abstract: A method for forming a wafer level package by incorporating an insulating pad of an elastic material under a dummy plug is described. In the method, a multiplicity of pads or islands formed of an elastic material is first formed on a pre-processed semiconductor substrate before a multiplicity of dummy via plugs are formed on top. The dummy via plugs are used as a support structure for building I/O redistribution lines (i.e. metal traces) thereon such that I/O bond pads may be built for supporting solder bumps or solder balls. The multiplicity of insulating pads is used for stress relief during a bonding process with the solder ball built on top without the conventional defect of cracking due to high elasticity of the material when a large area insulating layer is deposited on top.
    Type: Grant
    Filed: June 16, 2000
    Date of Patent: March 19, 2002
    Assignee: Industrial Technology Research Institute
    Inventors: Szu-Wei Lu, Kuo-Chuan Chen, Jyh-Rong Lin, Ruoh-Huey Wang, Hsu-Tien Hu, Hsin-Chien Huang
  • Patent number: 6179200
    Abstract: A method for forming solder balls that have improved height on an electronic substrate such as a silicon wafer and devices formed are disclosed. In the method, after solder bumps are deposited by a conventional method such as evaporation, electroplating, electroless plating or solder paste screen printing, the solder bumps are reflown on the substrate in an upside down position such that the gravity of the solder material pulls down the solder ball and thereby increasing its height after the reflow process is completed. It has been found that a minimum of 5%, and preferably about 10% height increase has been achieved. Another benefit achieved by the present invention novel method which is associated with the increase in the solder ball height is a corresponding increase in the pitch distance between the solder balls by at least 5%.
    Type: Grant
    Filed: February 3, 1999
    Date of Patent: January 30, 2001
    Assignee: Industrial Technology Research Institute
    Inventors: Ling-Chen Kung, Hsu-Tien Hu, Ruoh-Huey Uang, Szu-Wei Lu, Chun-Yi Kuo