Patents by Inventor Hsu Yang
Hsu Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240349493Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.Type: ApplicationFiled: June 26, 2024Publication date: October 17, 2024Applicants: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Yi-Wei Chen, Hsu-Yang Wang, Chun-Chieh Chiu, Shih-Fang Tzou
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Publication number: 20240324187Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.Type: ApplicationFiled: June 2, 2024Publication date: September 26, 2024Applicants: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Yi-Wei Chen, Hsu-Yang Wang, Chun-Chieh Chiu, Shih-Fang Tzou
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Patent number: 12058851Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.Type: GrantFiled: May 18, 2023Date of Patent: August 6, 2024Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Yi-Wei Chen, Hsu-Yang Wang, Chun-Chieh Chiu, Shih-Fang Tzou
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Patent number: 12014473Abstract: An intelligent zooming method and an electronic device using the same are provided. The intelligent zooming method includes the following steps. A text paragraph corresponding to the text is merged. The text paragraph is automatically arranged according to the text paragraph and a text magnification box. The text paragraph in the text magnification box is enlarged according to a text magnification ratio. A block group containing the block and other blocks connected thereto is merged. A block magnification ratio is adjusted according to the block group and a block magnification box. The block group in the block magnification box is enlarged according to the block magnification ratio. The picture is cropped to obtain an object. A picture magnification ratio is adjusted according to the object and a picture magnification box. The object in the picture magnification box is enlarged according to the picture magnification ratio.Type: GrantFiled: August 29, 2022Date of Patent: June 18, 2024Assignee: ACER INCORPORATEDInventors: En-Shin Chen, An-Cheng Lee, Hsu-Yang Chang, Ying-Shih Hung
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Patent number: 11800702Abstract: A method for forming a memory device includes the steps of providing a substrate, forming an isolation structure in the substrate to define a plurality of active regions in the substrate, the active regions respectively comprising two terminal portions and a central portion between the terminal portions, forming a plurality of island features on the substrate, wherein each of the island features covers two of the terminals portions respectively belonging to two of the active regions, performing a first etching process, using the island features as an etching mask to etch the substrate to define a plurality of island structures and a first recessed region surrounding the island structures on the substrate, and removing the island features to expose the island structures.Type: GrantFiled: March 16, 2021Date of Patent: October 24, 2023Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Hsu-Yang Wang, Ping-Cheng Hsu, Shih-Fang Tzou, Chin-Lung Lin, Yi-Hsiu Lee, Koji Taniguchi, Harn-Jiunn Wang, Tsung-Ying Tsai
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Publication number: 20230317459Abstract: Interconnect structures and methods and apparatuses for forming the same are disclosed. In an embodiment, a method includes supplying a process gas to a process chamber; igniting the process gas into a plasma in the process chamber; reducing a pressure of the process chamber to less than 0.3 mTorr; and after reducing the pressure of the process chamber, depositing a conductive layer on a substrate in the process chamber.Type: ApplicationFiled: June 8, 2023Publication date: October 5, 2023Inventors: Chun-Hsu Yang, Huei-Wen Hsieh, Nai-Hao Yang, Yu-Cheng Hsiao, Chun-Sheng Chen, Che-Wei Tien, Kuan-Chia Chen
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Publication number: 20230292498Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.Type: ApplicationFiled: May 18, 2023Publication date: September 14, 2023Applicants: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Yi-Wei Chen, Hsu-Yang Wang, Chun-Chieh Chiu, Shih-Fang Tzou
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Patent number: 11711916Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.Type: GrantFiled: January 29, 2021Date of Patent: July 25, 2023Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Yi-Wei Chen, Hsu-Yang Wang, Chun-Chieh Chiu, Shih-Fang Tzou
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Patent number: 11694899Abstract: Interconnect structures and methods and apparatuses for forming the same are disclosed. In an embodiment, a method includes supplying a process gas to a process chamber; igniting the process gas into a plasma in the process chamber; reducing a pressure of the process chamber to less than 0.3 mTorr; and after reducing the pressure of the process chamber, depositing a conductive layer on a substrate in the process chamber.Type: GrantFiled: June 9, 2020Date of Patent: July 4, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Hsu Yang, Chun-Sheng Chen, Nai-Hao Yang, Kuan-Chia Chen, Huei-Wen Hsieh, Yu-Cheng Hsiao, Che-Wei Tien
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Patent number: 11665888Abstract: A method for fabricating semiconductor device includes the steps of: forming a semiconductor layer on a substrate; removing part of the semiconductor layer and part of the substrate to form a trench; forming a liner in the trench; removing part of the liner to form a spacer adjacent to two sides of the trench; forming a conductive layer in the trench; forming a metal layer on the conductive layer; forming a mask layer on the metal layer; and patterning the mask layer, the metal layer, and the conductive layer to form a bit line structure.Type: GrantFiled: December 25, 2020Date of Patent: May 30, 2023Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Wei-Lun Hsu, Hung-Lin Shih, Che-Hung Huang, Ping-Cheng Hsu, Hsu-Yang Wang
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Publication number: 20230082451Abstract: An intelligent zooming method and an electronic device using the same are provided. The intelligent zooming method includes the following steps. A text paragraph corresponding to the text is merged. The text paragraph is automatically arranged according to the text paragraph and a text magnification box. The text paragraph in the text magnification box is enlarged according to a text magnification ratio. A block group containing the block and other blocks connected thereto is merged. A block magnification ratio is adjusted according to the block group and a block magnification box. The block group in the block magnification box is enlarged according to the block magnification ratio. The picture is cropped to obtain an object. A picture magnification ratio is adjusted according to the object and a picture magnification box. The object in the picture magnification box is enlarged according to the picture magnification ratio.Type: ApplicationFiled: August 29, 2022Publication date: March 16, 2023Applicant: Acer IncorporatedInventors: En-Shin CHEN, An-Cheng LEE, Hsu-Yang CHANG, Ying-Shih HUNG
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Publication number: 20220384255Abstract: Interconnect structures and methods and apparatuses for forming the same are disclosed. In an embodiment, a method includes supplying a process gas to a process chamber; igniting the process gas into a plasma in the process chamber; reducing a pressure of the process chamber to less than 0.3 mTorr; and after reducing the pressure of the process chamber, depositing a conductive layer on a substrate in the process chamber.Type: ApplicationFiled: August 9, 2022Publication date: December 1, 2022Inventors: Chun-Hsu Yang, Chun-Sheng Chen, Nai-Hao Yang, Kuan-Chia Chen, Huei-Wen Hsieh, Yu-Cheng Hsiao, Che-Wei Tien
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Publication number: 20210217622Abstract: Interconnect structures and methods and apparatuses for forming the same are disclosed. In an embodiment, a method includes supplying a process gas to a process chamber; igniting the process gas into a plasma in the process chamber; reducing a pressure of the process chamber to less than 0.3 mTorr; and after reducing the pressure of the process chamber, depositing a conductive layer on a substrate in the process chamber.Type: ApplicationFiled: June 9, 2020Publication date: July 15, 2021Inventors: Chun-Hsu Yang, Chun-Sheng Chen, Nai-Hao Yang, Kuan-Chia Chen, Huei-Wen Hsieh, Yu-Cheng Hsiao, Che-Wei Tien
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Publication number: 20210202492Abstract: A method for forming a memory device includes the steps of providing a substrate, forming an isolation structure in the substrate to define a plurality of active regions in the substrate, the active regions respectively comprising two terminal portions and a central portion between the terminal portions, forming a plurality of island features on the substrate, wherein each of the island features covers two of the terminals portions respectively belonging to two of the active regions, performing a first etching process, using the island features as an etching mask to etch the substrate to define a plurality of island structures and a first recessed region surrounding the island structures on the substrate, and removing the island features to expose the island structures.Type: ApplicationFiled: March 16, 2021Publication date: July 1, 2021Inventors: Hsu-Yang Wang, Ping-Cheng Hsu, Shih-Fang Tzou, Chin-Lung Lin, Yi-Hsiu Lee, Koji Taniguchi, Harn-Jiunn Wang, Tsung-Ying Tsai
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Publication number: 20210151442Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.Type: ApplicationFiled: January 29, 2021Publication date: May 20, 2021Inventors: Yi-Wei Chen, Hsu-Yang Wang, Chun-Chieh Chiu, Shih-Fang Tzou
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Publication number: 20210118889Abstract: A method for fabricating semiconductor device includes the steps of: forming a semiconductor layer on a substrate; removing part of the semiconductor layer and part of the substrate to form a trench; forming a liner in the trench; removing part of the liner to form a spacer adjacent to two sides of the trench; forming a conductive layer in the trench; forming a metal layer on the conductive layer; forming a mask layer on the metal layer; and patterning the mask layer, the metal layer, and the conductive layer to form a bit line structure.Type: ApplicationFiled: December 25, 2020Publication date: April 22, 2021Inventors: Wei-Lun Hsu, Hung-Lin Shih, Che-Hung Huang, Ping-Cheng Hsu, Hsu-Yang Wang
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Patent number: 10985166Abstract: A method for forming a memory device is disclosed, including providing a substrate, forming an isolation structure and plural active regions in the substrate, forming a plurality of island features on the substrate respectively covering two of the terminal portions of the active regions, using the island features as an etching mask to etch the substrate to perform a first etching process to define a first recessed region and plural island structures on the substrate. The island structures respectively comprise the two terminal portions of the active regions and the first recessed region comprises the central portions of the active regions.Type: GrantFiled: October 31, 2018Date of Patent: April 20, 2021Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Hsu-Yang Wang, Ping-Cheng Hsu, Shih-Fang Tzou, Chin-Lung Lin, Yi-Hsiu Lee, Koji Taniguchi, Harn-Jiunn Wang, Tsung-Ying Tsai
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Patent number: 10943909Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.Type: GrantFiled: June 7, 2018Date of Patent: March 9, 2021Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Yi-Wei Chen, Hsu-Yang Wang, Chun-Chieh Chiu, Shih-Fang Tzou
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Patent number: 10910386Abstract: According to an embodiment of the present invention, a method for fabricating semiconductor device includes the steps of: forming a semiconductor layer on a substrate; removing part of the semiconductor layer and part of the substrate to form a trench; forming a liner in the trench; removing part of the liner to form a spacer adjacent to two sides of the trench; and forming a bit line structure in the trench.Type: GrantFiled: April 3, 2018Date of Patent: February 2, 2021Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Wei-Lun Hsu, Hung-Lin Shih, Che-Hung Huang, Ping-Cheng Hsu, Hsu-Yang Wang
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Patent number: 10815724Abstract: A double-layer Roman shade folding structure includes a bracket. The bracket is provided with an outer curtain fabric, a roller tube, and an inner curtain fabric. The outer curtain fabric is provided with a plurality of strip-shaped limiting members that are arranged horizontally and spaced apart at equal intervals. An opening is defined between the limiting members and the outer curtain fabric for the inner curtain fabric to pass therethrough. When the bottom end of the inner curtain fabric drives the bottom end of the outer curtain fabric to be moved up, the plurality of limiting members are pushed and moved up in sequence so that the outer curtain fabric is folded and overlapped continuously.Type: GrantFiled: December 4, 2018Date of Patent: October 27, 2020Inventor: Sen-Hsu Yang