Patents by Inventor Hsu-Yang Lee

Hsu-Yang Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor package having a cavity structure
    Patent number: 8492883
    Abstract: A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, a plurality of leads, a chip, and a package body. The die pad includes: (1) a peripheral edge region defining, a cavity with a cavity bottom including a central portion; (2) an upper sloped portion; and (3) a lower sloped portion. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the central portion of the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: July 23, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Pao-Huei Chang Chien, Ping-Cheng Hu, Chien-Wen Chen, Hsu-Yang Lee
  • Advanced quad flat no lead chip package having a protective layer to enhance surface mounting and manufacturing methods thereof
    Patent number: 8115285
    Abstract: A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, multiple leads, a chip, a package body, and a protective layer. The die pad includes an upper sloped portion, a lower sloped portion, and a peripheral edge region defining a cavity with a cavity bottom. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body. The protective layer substantially covers the lower sloped portion and the lower surface of at least one lead.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: February 14, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien-Wen Chen, Yi-Shao Lai, Hsiao-Chuan Chang, Tsung-Yueh Tsai, Pao-Huei Chang Chien, Ping-Cheng Hu, Hsu-Yang Lee
  • ADVANCED QUAD FLAT NO LEAD CHIP PACKAGE HAVING A CAVITY STRUCTURE AND MANUFACTURING METHODS THEREOF
    Publication number: 20090230523
    Abstract: A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, a plurality of leads, a chip, and a package body. The die pad includes: (1) a peripheral edge region defining, a cavity with a cavity bottom including a central portion; (2) an upper sloped portion; and (3) a lower sloped portion. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the central portion of the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body.
    Type: Application
    Filed: August 15, 2008
    Publication date: September 17, 2009
    Inventors: Pao-Huei Chang Chien, Ping-Cheng Hu, Chien-Wen Chen, Hsu-Yang Lee