Abstract: The invention provides a gate driving circuit and a display apparatus. The gate driving circuit includes 1st to Nth stage shift registers for respectively generating and sequentially outputting 1st to Nth stage scan signals to the display panel, where N is an integer greater than or equal to 4. Each of the shift registers is configured to receive a starting signal, and the starting signal is utilized to trigger the 1st and 2nd stage shift registers to generate the 1st and 2nd stage scan signals respectively, and the starting signal is utilized to reset the 3rd to Nth stage shift registers.

Abstract: In a display panel, multiple first alignment patterns are disposed in a non-display area on a first substrate, and each first alignment pattern includes a first portion and a second portion connected to each other. Multiple second alignment patterns are disposed in the non-display area on a second substrate, and each of the second alignment patterns includes a third portion and a fourth portion. There is a first length difference between the length of each first portion along a first direction and the length of the corresponding third portion along the first direction, and the first length differences are different from each other. There is a second length difference between the length of each second portion along a second direction and the length of the corresponding fourth portion along the second direction, and the second length differences are different from each other.

Abstract: An electronic product includes a substrate and a bonding pad structure. The bonding pad structure is disposed on the substrate, and the bonding pad structure includes a first metal layer, a first insulating layer, at least one first connecting hole and a transparent conductive layer. The first metal layer and the first insulating layer are disposed on the substrate. The first connecting hole is situated in the first insulating layer, and the first connecting hole exposes a portion of the first metal layer. The transparent conductive layer is disposed on the first insulating layer, and the transparent conductive layer has a first edge and a second edge opposite to the first edge, wherein the transparent conductive layer is electrically connected to the first metal layer through the first connecting hole. A spacing between the first edge and the first connecting hole is greater than or equal to 100 ?m.

Abstract: An electronic device includes a first substrate, a second substrate, a plurality of first metal line segments and a shielding layer. The second substrate is opposite to the first substrate. The first metal line segments are disposed on the first substrate and extend along a first direction, wherein at least one of the first metal line segments includes a first alignment part and a first trace part, a width of the first alignment part is larger than a width of the first trace part, and the first alignment parts are arranged along a second direction. The shielding layer is disposed on the second substrate, and the shielding layer includes a plurality of first alignment structures, wherein one of the first alignment parts is aligned with one of the first alignment structures in a normal vector of the first substrate.

Abstract: A display panel including a first substrate, a second substrate opposite to the first substrate, and a display medium located between the first substrate and the second substrate is provided. The display panel further includes a plurality of pixel structures, a plurality of data lines and a plurality of scan lines electrically connected to the pixel structures, a first driving unit located at a peripheral area, at least one test line, and at least one first pad located at the peripheral area. Each of the data lines has a first end and a second end opposite to each other. The first driving unit is electrically connected to the first ends of the data lines. The at least one test line is electrically connected to the second ends of at least part of the data lines. The at least one test line is grounded through the at least one first pad.

Abstract: A display panel is provided, and includes a first substrate, a connecting structure, a passivation layer, a second substrate and a sealant. The first substrate has an active area and a peripheral area. The connecting structure is disposed on the first substrate and located in the peripheral area, and is configured to electrically connect different metal layers. The passivation layer is disposed on and covers the connecting structure. The second substrate is disposed opposite to the first substrate. The sealant is sandwiched between the first substrate and the second substrate. In the display panel, a vertical projection of the sealant on the first substrate and a vertical projection of the connecting structure on the first substrate are overlapped.

Abstract: The present invention relates to a display panel and a gate driving circuit of the display panel. The gate driving circuit is disposed on a first substrate and includes a first transistor unit. The first transistor unit is disposed on the first substrate and includes a first gate block, a second gate block, and a first connection portion. The first connection portion is electrically connected to the first gate block and the second gate block. At least a gap is formed between the first gate block and the second gate block. The display panel includes the first substrate, the gate driving circuit, a second substrate, and a sealant. The second substrate is disposed corresponding to the first substrate. The sealant is formed between the first substrate and the second substrate.

Abstract: In a shift register, a pre-charge unit is configured to receive a first input signal and output a pre-charge signal to a first node, a pull-up unit is configured to output a scan signal to a second node, and a pull-down unit is configured to receive a pull-down control signal. The pull-down control signal switches from a disable voltage to an enable voltage before the display panel switches from a non-display status to a display status.

Abstract: A thin film transistor substrate having a display region and a peripheral region, and the thin film transistor substrate includes a first substrate, scan lines, data lines, an insulating layer, first thin film transistors, at least one passivation layer and at least one gate driving circuit. The first substrate has an electrostatic protection area and a driving circuit area, and the electrostatic protection area and the driving circuit area are situated in the peripheral region. The scan lines, the data lines and the first thin film transistors are disposed in the display region. The insulating layer includes a gate insulator of the first thin film transistor, and the passivation layer is disposed on the insulating layer. The gate driving circuit is disposed in the driving circuit area. At least one of the passivation layer and the insulating layer are not disposed in the electrostatic protection area.

Abstract: A shift register circuit is disclosed. The shift register circuit includes a first gate driving module, a second gate driving module, a first discharging module, and a second discharging module. The first gate driving module has a first node and a first output terminal. The second gate driving module has a second node and a second output terminal. The first discharging module is coupled to the first node, the second node, and the first output terminal respectively. The second discharging module is coupled to the second node, the first node, and the second output terminal respectively. Both the first discharging module and the second discharging module include ten transistors respectively.

Abstract: A shift register includes a primary circuit and a secondary circuit including an inverting circuit and a pull-down circuit. The pull-down circuit includes a first transistor. The primary circuit has an output terminal, a first and a second input terminals, and is electrically connected to a first common terminal. The secondary circuit is electrically connected to the first common terminal. The pull-down circuit is electrically connected to the inverting circuit. The first transistor has a first top gate, a first bottom gate, a first first electrode and a first second electrode, wherein the first second electrode is configured to receive a first voltage level, the first top gate is configured to receive a second voltage level, and the second voltage level is higher than the first voltage level.

Abstract: A shift register and a display device are provided. The shift register includes a pre-charge unit, a pull-up unit, a first pull-down unit and a second pull-down unit. The pre-charge unit receives first and second input signals, and outputs a pre-charge signal via a first node. The pull-up unit receives the pre-charge signal and a clock signal, and outputs a scanning signal via a second node. The first pull-down unit receives the pre-charge signal, first and second pull-down control signals, and controls whether to pull-down the scanning signal to a reference voltage level. The second pull-down unit receives the pre-charge signal and first and second pull-down control signals, and controls whether to keep the scanning signal at the reference voltage level. The period of the first second pull-down control signal and the period of the second pull-down control signal are in a range from 12 frames to 180 frames.

Abstract: A pixel structure includes a first substrate, a thin-film transistor, a second insulation layer, a first transparent conduction layer and a second substrate. The thin-film transistor includes a gate electrode formed on the first substrate, a semiconductor layer formed on the gate electrode, a first insulation layer located between the semiconductor layer and the gate electrode, and an electrode layer including a source electrode and a drain electrode. The source electrode covers a portion of the semiconductor layer. The drain electrode covers a portion of the semiconductor layer. The second insulation layer covers the thin-film transistor. The first transparent conduction layer is formed on the second insulation layer. An opening is formed in the first transparent conduction layer along a fringe of the semiconductor layer.

Abstract: A display panel is provided, and includes a first substrate, a connecting structure, a passivation layer, a second substrate and a sealant. The first substrate has an active area and a peripheral area. The connecting structure is disposed on the first substrate and located in the peripheral area, and is configured to electrically connect different metal layers, The passivation layer is disposed on and covers the connecting structure. The second substrate is disposed opposite to the first substrate. The sealant is sandwiched between the first substrate and the second substrate. In the display panel, a vertical projection of the sealant on the first substrate and a vertical projection of the connecting structure on the first substrate are overlapped.

Abstract: A display panel including a first substrate, a plurality of pixel units disposed on the first substrate and a shielding layer is provided. Each pixel unit includes a thin-film transistor, a first signal line and a second signal line electrically connected to the thin-film transistor. The shielding layer includes a first portion located on a peripheral region and a second portion located on a non-rectangular display region. An inner contour of an orthogonal projection of the first portion of the shielding layer on the first substrate includes a plurality of first line segments and a plurality of second line segments. The first line segments are parallel to orthogonal projections of the first signal lines on the first substrate. The second line segments are respectively parallel to orthogonal projections of the second signal lines on the first substrate.

Abstract: A display panel including a first substrate, a plurality of pixel units disposed on the first substrate and a shielding layer is provided. Each pixel unit includes a thin-film transistor, a first signal line and a second signal line electrically connected to the thin-film transistor. The shielding layer includes a first portion located on a peripheral region and a second portion located on a non-rectangular display region. An inner contour of an orthogonal projection of the first portion of the shielding layer on the first substrate includes a plurality of first line segments and a plurality of second line segments. The first line segments are parallel to orthogonal projections of the first signal lines on the first substrate. The second line segments are respectively parallel to orthogonal projections of the second signal lines on the first substrate.

Abstract: The invention provides a gate driving circuit and a display apparatus. The gate driving circuit includes 1st to Nth stage shift registers for respectively generating and sequentially outputting 1st to Nth stage scan signals to the display panel, where N is an integer greater than or equal to 4. Each of the shift registers is configured to receive a starting signal, and the starting signal is utilized to trigger the 1st and 2nd stage shift registers to generate the 1st and 2nd stage scan signals respectively, and the starting signal is utilized to reset the 3rd to Nth stage shift registers.

Abstract: The invention discloses a gate driving circuit and a display device. The gate driving circuit includes first to eighth dock signal lines and first to Nth stage first shift registers, where N is an integer greater than or equal to 9. The first to eighth clock signal lines are configured to provide first to eighth clock signals, respectively. The ith stage first shift register is coupled to one of the first to eighth clock signal lines and receives one of the first to eighth clock signals, a first input signal and a second input signal and outputs an ith stage first output signal, where i is any integer from 1 to N.

Abstract: A display device and a method for manufacturing the same are provided. The display device includes a first substrate, a second substrate and a light curable sealant. The first substrate has a displaying area and a non-displaying area, in which the displaying area includes a pixel array, and the non-displaying area includes a driving circuit. The driving circuit includes at least a capacitor which is made of transparent conductive material. The second substrate has an opaque area. The light curable sealant is located between the first substrate and the second substrate. When viewing from a normal vector of the first substrate or the second substrate, the light curable sealant, the capacitor and the opaque area are at least partially overlapped with each other.

Abstract: A display device and a method for manufacturing the same are provided. The display device includes a first substrate, a second substrate and a light curable sealant. The first substrate has a displaying area and a non-displaying area, in which the displaying area includes a pixel array, and the non-displaying area includes a driving circuit. The driving circuit includes at least a capacitor which is made of transparent conductive material. The second substrate has an opaque area. The light curable sealant is located between the first substrate and the second substrate. When viewing from a normal vector of the first substrate or the second substrate, the light curable sealant, the capacitor and the opaque area are at least partially overlapped with each other.