Abstract: An extensible host controller applied to a host includes a universal serial bus (USB) module, a control unit, and a peripheral component interconnect express (PCIE) bus. The USB module includes a USB unit and a predetermined unit. The PCIE bus is coupled to the control unit, wherein the PCIE bus supports a USB mode and a predetermined mode. When a first host with a first extensible host controller is connected to the USB module, the control unit makes the host utilize the USB mode and the USB unit, or the predetermined mode and the predetermined unit to communicate with the first host according to a determination way.

Abstract: An activation method of a universal serial bus (USB) compatible flash device is disclosed, wherein the USB compatible flash device includes a controller and a pair of signal pins, and the controller includes a memory and a microprocessor. The activation method includes when the USB compatible flash device is coupled to a host, the pair of signal pins receiving a pair of predetermined signals, and transmitting the pair of predetermined signals to the microprocessor, wherein the pair of signal pins are different from a power line pin and a ground pin of the USB compatible flash device; when the microprocessor receives the pair of predetermined signals through the pair of signal pins, the microprocessor determining that a force event occurs; and after the microprocessor determines that the force event occurs, the microprocessor activating the USB compatible flash device according to an original activation program stored in the memory.

Abstract: An extensible host controller applied to a host includes a universal serial bus (USB) module, a control unit, and a peripheral component interconnect express (PCIE) bus. The USB module includes a USB unit and a predetermined unit. The PCIE bus is coupled to the control unit, wherein the PCIE bus supports a USB mode and a predetermined mode. When a first host with a first extensible host controller is connected to the USB module, the control unit makes the host utilize the USB mode and the USB unit, or the predetermined mode and the predetermined unit to communicate with the first host according to a determination way.

Abstract: A circuit includes an oversampling logic unit, an alternating current estimator, and a logic processor. The oversampling logic unit generates a plurality of alternating current terms according to an oversampling clock, and outputs a plurality of alternating current terms corresponding to an output clock from the plurality of alternating current terms according to the output clock. The alternating current estimator executes a discrete cosine transform and a discrete sine transform on a plurality of alternating current terms outputted from the oversampling logic unit within a first predetermined time to generate a first value and a second value respectively. The logic processor compares a number of first values and a number of second values within a second predetermined time, and generates a clock data recovery phase locked indicator according to a comparing result.

Abstract: A circuit for simultaneously analyzing performance and bugs includes a mapping unit and a USB 3.0 data flow analyzer. The mapping unit is used for mapping commands transmitted to a USB 3.0 host through a peripheral component interconnect express and internal events of the USB 3.0 host to a packet of a USB 3.0 bus. The USB 3.0 data flow analyzer is used for analyzing performance and bugs of the USB 3.0 host through the packet of the USB 3.0 bus.

Abstract: A circuit for simultaneously analyzing performance and bugs includes a mapping unit and a USB 3.0 data flow analyzer. The mapping unit is used for mapping commands transmitted to a USB 3.0 host through a peripheral component interconnect express and internal events of the USB 3.0 host to a packet of a USB 3.0 bus. The USB 3.0 data flow analyzer is used for analyzing performance and bugs of the USB 3.0 host through the packet of the USB 3.0 bus.

Abstract: A system of realizing RAID-1 on a portable storage medium includes a Universal Serial Bus device and the portable storage medium. The portable storage medium is divided into a main partition and at least one backup partition according to a RAID-1 mode. The Universal Serial Bus device is coupled to the portable storage medium for receiving a write command and/or a read command transmitted by a host, and writing data to the portable storage medium and/or reading data from the portable storage medium according to the write command and/or the read command. The Universal Serial Bus device does not transmit capacity information of the at least one backup partition to the host.

Abstract: A circuit includes an oversampling logic unit, an alternating current estimator, and a logic processor. The oversampling logic unit generates a plurality of alternating current terms according to an oversampling clock, and outputs a plurality of alternating current terms corresponding to an output clock from the plurality of alternating current terms according to the output clock. The alternating current estimator executes a discrete cosine transform and a discrete sine transform on a plurality of alternating current terms outputted from the oversampling logic unit within a first predetermined time to generate a first value and a second value respectively. The logic processor compares a number of first values and a number of second values within a second predetermined time, and generates a clock data recovery phase locked indicator according to a comparing result.

Abstract: A computer system and a method of signal transmission via a PCI-Express bus is provided for transmitting a power-saving signal among a plurality of peripheral devices. For the peripheral devices coupled with the system chips can enter a power-saving mode successfully, a signal snooping and blocking manners are introduced into the system chips. The present invention is to improve on a problem that the system chips cannot enter the power-saving mode simultaneously since the system chips don't set any power-management unit therein.

Abstract: A method for transmitting a power-saving command between a computer system and system chips thereof is described. A power-saving command associated with a first system chip is introduced to the computer system since a BIOS is modified therefore. The CPU of the computer system determines the power mode of the first system chip according to a register therein. As the first system chip enters the power-saving mode, the second system chip is informed entering the power-saving mode as well. Therefore, the peripheral devices coupled to the system chips can enter the power-saving mode smoothly so as to solve that the devices cannot enter the mode simultaneously since there is no power management unit (PMU) installed in the first system chip.

Abstract: A PCI-Express bus is incorporated in a method for transmitting a power-saving command between a computer system and its plurality of peripheral devices of the present invention. More particularly, a specific power management command is introduced into the signal transmission protocol of a system command, which is transmitted between the plural system chips. Therefore, the peripheral devices coupled with the system chips can enter a certain power mode simultaneously. The present invention is used to solve the problem of the peripheral devices cannot enter the certain power mode since the system chip has no power management unit disposed under the PCI-Express structure.

Abstract: A PCI-Express bus is incorporated in a method for transmitting a power-saving command between a computer system and its plurality of peripheral devices of the present invention. More particularly, a specific power management command is introduced into the signal transmission protocol of a system command, which is transmitted between the plural system chips. Therefore, the peripheral devices coupled with the system chips can enter a certain power mode simultaneously. The present invention is used to solve the problem of the peripheral devices cannot enter the certain power mode since the system chip has no power management unit disposed under the PCI-Express structure.

Abstract: A computer system and a method of signal transmission via a PCI-Express bus is provided for transmitting a power-saving signal among a plurality of peripheral devices. For the peripheral devices coupled with the system chips can enter a power-saving mode successfully, a signal snooping and blocking manners are introduced into the system chips. The present invention is to improve on a problem that the system chips cannot enter the power-saving mode simultaneously since the system chips don't set any power-management unit therein.

Abstract: A method for transmitting a power-saving command between a computer system and system chips thereof is described. A power-saving command associated with a first system chip is introduced to the computer system since a BIOS is modified therefore. The CPU of the computer system determines the power mode of the first system chip according to a register therein. As the first system chip enters the power-saving mode, the second system chip is informed entering the power-saving mode as well. Therefore, the peripheral devices coupled to the system chips can enter the power-saving mode smoothly so as to solve that the devices cannot enter the mode simultaneously since there is no power management unit (PMU) installed in the first system chip.

Abstract: The present invention relates to both of a bi-stage correlation calculation demodulation system, and a fast walsh block demodulation device at a receiver, wherein the bi-stage correlation calculation demodulation system has a characteristic of bi-stage correlation calculation in which the subsequent second-stage correlation calculations are dependent on the first-stage correlation calculation results by utilizing an incomplete orthogonal property within CCK codewords to arrange the CCK codewords operated in the first-stage correlation calculations and second-stage correlation calculations properly and respectively.

Abstract: A complementary code keying (CCK) demodulation system is disclosed, and more particularly relates to both of a bi-stage correlation calculation demodulation system, and a fast walsh block demodulation device at a receiver, wherein the bi-stage correlation calculation demodulation system has a characteristic of bi-stage correlation calculation in which the subsequent second-stage correlation calculations are dependent on the first-stage correlation calculation results by utilizing an incomplete orthogonal property within CCK codewords to arrange the CCK codewords operated in the first-stage correlation calculations and second-stage correlation calculations properly and respectively. Thus, the operation quantities of correlation calculations are reduced substantially, and the codeword transmitted from transmitter is resolved rapidly, so that the complexity of receiver is decreased and the demodulating speed is speeded up.