Patents by Inventor Hsuan-Hsu Chen

Hsuan-Hsu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10937893
    Abstract: A manufacturing method of a semiconductor device includes the following steps. First patterned structures are formed on a substrate. Each of the first patterned structures includes a first semiconductor pattern and a first bottom protection pattern disposed between the first semiconductor pattern and the substrate. A first protection layer is formed on the first patterned structures and the substrate. A part of the first protection layer is located between the first patterned structures. A first opening is formed in the first protection layer between the first patterned structures. The first opening penetrates the first protection layer and exposes a part of the substrate. A first etching process is performed after forming the first opening. A part of the substrate under the first patterned structures is removed by the first etching process for suspending at least a part of each of the first patterned structures above the substrate.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: March 2, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chuan-Chang Wu, Zhen Wu, Hsuan-Hsu Chen, Chun-Lung Chen
  • Publication number: 20210013325
    Abstract: A manufacturing method of a semiconductor device includes the following steps. First patterned structures are formed on a substrate. Each of the first patterned structures includes a first semiconductor pattern and a first bottom protection pattern disposed between the first semiconductor pattern and the substrate. A first protection layer is formed on the first patterned structures and the substrate. A part of the first protection layer is located between the first patterned structures. A first opening is formed in the first protection layer between the first patterned structures. The first opening penetrates the first protection layer and exposes a part of the substrate. A first etching process is performed after forming the first opening. A part of the substrate under the first patterned structures is removed by the first etching process for suspending at least a part of each of the first patterned structures above the substrate.
    Type: Application
    Filed: August 19, 2019
    Publication date: January 14, 2021
    Inventors: Chuan-Chang Wu, Zhen Wu, Hsuan-Hsu Chen, Chun-Lung Chen
  • Patent number: 10650204
    Abstract: A barcode detection method includes acquiring an image by a camera, acquiring a horizontal gradient and a vertical gradient of each pixel of the image within a region, generating a gradient phase and gradient magnitude of each pixel according to the horizontal gradient and the vertical gradient, performing a binarization process to the gradient magnitude of each pixel of the image within the region for generating a binarized image, vertically and horizontally sampling the binarized image for generating the gray level flip count in a vertical direction and a horizontal direction, locating an image region of a barcode according to the gray level flip count in the vertical direction and the horizontal direction, acquiring a plurality of gradient phases of all pixels within the image region for generating a gradient phase distribution, and generating a barcode format detection result according to the gradient phase distribution.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: May 12, 2020
    Assignee: WELTREND SEMICONDUCTOR INC.
    Inventors: Hsuan-Ying Chen, Hung-Chih Chiang, Ian Hsu
  • Publication number: 20190377918
    Abstract: A barcode detection method includes acquiring an image by a camera, acquiring a horizontal gradient and a vertical gradient of each pixel of the image within a region, generating a gradient phase and gradient magnitude of each pixel according to the horizontal gradient and the vertical gradient, performing a binarization process to the gradient magnitude of each pixel of the image within the region for generating a binarized image, vertically and horizontally sampling the binarized image for generating the gray level flip count in a vertical direction and a horizontal direction, locating an image region of a barcode according to the gray level flip count in the vertical direction and the horizontal direction, acquiring a plurality of gradient phases of all pixels within the image region for generating a gradient phase distribution, and generating a barcode format detection result according to the gradient phase distribution.
    Type: Application
    Filed: August 14, 2018
    Publication date: December 12, 2019
    Inventors: Hsuan-Ying Chen, Hung-Chih Chiang, Ian Hsu
  • Patent number: 9876116
    Abstract: A semiconductor structure and a manufacturing method for the same are disclosed. The semiconductor structure includes a first gate structure, a second gate structure and a second dielectric spacer. Each of the first gate structure and the second gate structure adjacent to each other includes a first dielectric spacer. The second dielectric spacer is on one of opposing sidewalls of the first gate structure and without being disposed on the dielectric spacer of the second gate structure.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: January 23, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ping Wang, Jyh-Shyang Jenq, Yu-Hsiang Lin, Hsuan-Hsu Chen, Chien-Hao Chen, Yi-Han Ye
  • Publication number: 20170271504
    Abstract: A semiconductor structure and a manufacturing method for the same are disclosed. The semiconductor structure includes a first gate structure, a second gate structure and a second dielectric spacer. Each of the first gate structure and the second gate structure adjacent to each other includes a first dielectric spacer. The second dielectric spacer is on one of opposing sidewalls of the first gate structure and without being disposed on the dielectric spacer of the second gate structure.
    Type: Application
    Filed: June 8, 2017
    Publication date: September 21, 2017
    Inventors: Yu-Ping Wang, Jyh-Shyang Jenq, Yu-Hsiang Lin, Hsuan-Hsu Chen, Chien-Hao Chen, Yi-Han Ye
  • Patent number: 9711368
    Abstract: A sidewall image transfer (SIT) process is provided. First, a substrate is provided. A sacrificial layer having a pattern is formed on the substrate. A first measuring step is performed to measure a width of the pattern of the sacrificial layer. A material layer is formed conformally on the sacrificial layer, wherein a thickness of the material layer is adjusted according to the result of the first measuring step. Then, the material layer is removed anisotropically, so the material layer becomes a spacer on a sidewall of the sacrificial layer. Lastly, the sacrificial layer is removed.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: July 18, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Lung-En Kuo, Po-Wen Su, Chen-Yi Weng, Hsuan-Hsu Chen
  • Patent number: 9711646
    Abstract: A semiconductor structure and a manufacturing method for the same are disclosed. The semiconductor structure includes a first gate structure, a second gate structure and a second dielectric spacer. Each of the first gate structure and the second gate structure adjacent to each other includes a first dielectric spacer. The second dielectric spacer is on one of opposing sidewalls of the first gate structure and without being disposed on the dielectric spacer of the second gate structure.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: July 18, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ping Wang, Jyh-Shyang Jenq, Yu-Hsiang Lin, Hsuan-Hsu Chen, Chien-Hao Chen, Yi-Han Ye
  • Patent number: 9385000
    Abstract: A method of performing an etching process is provided. A substrate is provided, wherein a first region and a second region are defined on the substrate, and an overlapping region of the first region and the second region is defined as a third region. A tri-layer structure comprising an organic layer, a bottom anti-reflection coating (BARC), and a photoresist layer is formed on the substrate. The photoresist layer and the BARC in the second region are removed. An etching process is performed to remove the organic layer in the second region by using the BARC and/or the photoresist layer as a mask, wherein the etching process uses an etchant comprises CO2.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: July 5, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chieh-Te Chen, Feng-Yi Chang, Hsuan-Hsu Chen
  • Patent number: 9349812
    Abstract: A semiconductor device with a self-aligned contact and a method of manufacturing the same, wherein the method comprises the step of forming a 1st dielectric layer on gate structures, form a self-aligned contact trench between two gate structures, forming an 2nd dielectric layer on the 1st dielectric layer and in the self-aligned contact trench; patterning the 2nd dielectric layer into a 1st portion on the 1st dielectric layer and a 2nd portion filling in the self-aligned contact trench, using the 2nd dielectric layer as a mask to etch the 1st dielectric layer, and forming a metal layer and a self-aligned contact simultaneously in the 1st dielectric layer and in the self-aligned contact trench.
    Type: Grant
    Filed: May 27, 2013
    Date of Patent: May 24, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chieh-Te Chen, Feng-Yi Chang, Hsuan-Hsu Chen
  • Patent number: 9312365
    Abstract: The present invention provides a non-planar FET which includes a substrate, a fin structure, a sub spacer, a gate, a dielectric layer and a source/drain region. The fin structure is disposed on the substrate. The sub spacer is disposed only on a middle sidewall of the fin structure. The gate is disposed on the fin structure. The dielectric layer is disposed between the fin structure and the gate. The source/drain region is disposed in the fin structure. The present invention further provides a method of forming the same.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: April 12, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Hung Tsai, Ssu-I Fu, Ying-Tsung Chen, Chih-Wei Chen, Ying-Chih Lin, Chien-Ting Lin, Hsuan-Hsu Chen
  • Patent number: 9230812
    Abstract: A method for forming a semiconductor structure having an opening is provided. First, a substrate is provided, wherein a first region and a second region are defined on the substrate and an overlapping area of the first region and the second region is defined as a third region. A pattern density of the first region is substantially greater than that of the second region. Then, a material layer is formed on the substrate. A first hard mask and a second hard mask are formed on the material layer. The first hard mask in the first region is removed to form a patterned first hard mask. The second hard mask in the third region is removed to form a patterned second hard mask. Lastly, the material layer is patterned by using the patterned second hard mask layer as a mask to form at least an opening in the third region only.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: January 5, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chieh-Te Chen, Yu-Tsung Lai, Hsuan-Hsu Chen, Feng-Yi Chang
  • Publication number: 20150279957
    Abstract: A semiconductor structure and a manufacturing method for the same are disclosed. The semiconductor structure includes a first gate structure, a second gate structure and a second dielectric spacer. Each of the first gate structure and the second gate structure adjacent to each other includes a first dielectric spacer. The second dielectric spacer is on one of opposing sidewalls of the first gate structure and without being disposed on the dielectric spacer of the second gate structure.
    Type: Application
    Filed: March 31, 2014
    Publication date: October 1, 2015
    Applicant: United Microelectronics Corp.
    Inventors: Yu-Ping Wang, Jyh-Shyang Jenq, Yu-Hsiang Lin, Hsuan-Hsu Chen, Chien-Hao Chen, Yi-Han Ye
  • Patent number: 9117909
    Abstract: A method of forming a fin structure is provided. First, a substrate is provided, wherein a first region, a second region encompassing the first region, and a third region encompassing the second region are defined on the substrate. Then, a plurality of first trenches having a first depth are formed in the first region and the second region, wherein each two first trenches defines a first fin structure. The first fin structure in the second region is removed. Lastly, the first trenches are deepened to form a plurality of second trenches having a second depth, wherein each two second trenches define a second fin structure. The present invention further provides a structure of a non-planar transistor.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: August 25, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Lung-En Kuo, Po-Wen Su, Chen-Yi Weng, Hsuan-Hsu Chen
  • Publication number: 20150214068
    Abstract: A method of performing an etching process is provided. A substrate is provided, wherein a first region and a second region are defined on the substrate, and an overlapping region of the first region and the second region is defined as a third region. A tri-layer structure comprising an organic layer, a bottom anti-reflection coating (BARC), and a photoresist layer is formed on the substrate. The photoresist layer and the BARC in the second region are removed. An etching process is performed to remove the organic layer in the second region by using the BARC and/or the photoresist layer as a mask, wherein the etching process uses an etchant comprises CO2.
    Type: Application
    Filed: January 24, 2014
    Publication date: July 30, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chieh-Te Chen, Feng-Yi Chang, Hsuan-Hsu Chen
  • Patent number: 9023708
    Abstract: A method of forming a semiconductor device is provided. At least one gate structure including a dummy gate is formed on a substrate. A contact etch stop layer and a dielectric layer are formed to cover the gate structure. A portion of the contact etch stop layer and a portion of the dielectric layer are removed to expose the top of the gate structure. A dry etching process is performed to remove a portion of the dummy gate of the gate structure. A hydrogenation treatment is performed to the surface of the remaining dummy gate. A wet etching process is performed to remove the remaining dummy gate and thereby form a gate trench.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: May 5, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Li-Chiang Chen, Jiunn-Hsiung Liao, Hsuan-Hsu Chen, Feng-Yi Chang, Chieh-Te Chen, Shang-Yuan Tsai, Ching-Pin Hsu
  • Patent number: 9013024
    Abstract: A semiconductor structure includes a substrate, a recess and a material. The recess is located in the substrate, wherein the recess has an upper part and a lower part. The minimum width of the upper part is larger than the maximum width of the lower part. The material is located in the recess.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: April 21, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Ying-Chih Lin, Hsuan-Hsu Chen, Jiunn-Hsiung Liao, Lung-En Kuo
  • Patent number: 8993433
    Abstract: The present invention provides a manufacturing method of a semiconductor device, at least containing the following steps: first, a substrate is provided, wherein a first dielectric layer is formed on the substrate, at least one metal gate is formed in the first dielectric layer and at least one source drain region (S/D region) is disposed on two sides of the metal gate, at least one first trench is then formed in the first dielectric layer, exposing parts of the S/D region. The manufacturing method for forming the first trench further includes performing a first photolithography process through a first photomask and performing a second photolithography process through a second photomask, and at least one second trench is formed in the first dielectric layer, exposing parts of the metal gate, and finally, a conductive layer is filled in each first trench and each second trench.
    Type: Grant
    Filed: May 27, 2013
    Date of Patent: March 31, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chieh-Te Chen, Yu-Tsung Lai, Hsuan-Hsu Chen, Feng-Yi Chang, Chih-Sen Huang, Ching-Wen Hung
  • Publication number: 20150004766
    Abstract: The present invention provides a non-planar FET which includes a substrate, a fin structure, a sub spacer, a gate, a dielectric layer and a source/drain region. The fin structure is disposed on the substrate. The sub spacer is disposed only on a middle sidewall of the fin structure. The gate is disposed on the fin structure. The dielectric layer is disposed between the fin structure and the gate. The source/drain region is disposed in the fin structure. The present invention further provides a method of forming the same.
    Type: Application
    Filed: September 16, 2014
    Publication date: January 1, 2015
    Inventors: Shih-Hung Tsai, Ssu-I Fu, Ying-Tsung Chen, Chih-Wei Chen, Ying-Chih Lin, Chien-Ting Lin, Hsuan-Hsu Chen
  • Patent number: 8916475
    Abstract: A patterning method is provided. A mask composite layer and a first tri-layer photoresist are sequentially formed on a target layer. A first etching is performed to the mask composite layer, using the first tri-layer photoresist as a mask, to form at least one first opening in an upper portion of the mask composite layer. The first tri-layer photoresist is removed. A second tri-layer photoresist is formed on the mask composite layer. A second etching is performed to the mask composite layer, using the second tri-layer photoresist as a mask, to form at least one second opening in the upper portion of the mask composite layer. The second tri-layer photoresist is removed. A lower portion of the mask composite layer is patterned by using the upper portion of the mask composite layer as a mask. The target layer is patterned by using the patterned mask composite layer as a mask.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: December 23, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chieh-Te Chen, Feng-Yi Chang, Hsuan-Hsu Chen, Cheng-Hsing Chuang