Abstract: A display device includes a backboard, a rubber frame and a display panel. A backboard includes a base and a wall having a first end and a second end opposite to the first end. The first end connects with an edge of the base. The rubber frame includes an abutting portion, a supporting portion and an extending portion. The abutting portion locates outside the backboard and abuts against the wall. The supporting portion connects with the abutting portion and is supported at the second end. The extending portion connects with the abutting portion and extends toward outside from the backboard. The extending portion and the supporting portion are at least partially coplanar to define a connecting surface. The display panel couples with the connecting surface. An edge of the extending portion substantially aligns with or exceeds relative to the wall an edge of the display panel.

Abstract: An apparatus including; a substrate; an isolator that is formed over the substrate, the isolator including a silicon shield layer that is formed between a first buried oxide (BOX) layer and a second BOX layer; a silicon layer having an oxide trench structure formed therein, the oxide trench structure being arranged to define a first silicon island and a second silicon island; a first electronic circuit that is formed over the first silicon island; and a second electronic circuit that is formed over the second silicon island, the first electronic circuit being electrically coupled to the first electronic circuit.

Abstract: A display device includes a backboard, a rubber frame and a display panel. A backboard includes a base and a wall having a first end and a second end opposite to the first end. The first end connects with an edge of the base. The rubber frame includes an abutting portion, a supporting portion and an extending portion. The abutting portion locates outside the backboard and abuts against the wall. The supporting portion connects with the abutting portion and is supported at the second end. The extending portion connects with the abutting portion and extends toward outside from the backboard. The extending portion and the supporting portion are at least partially coplanar to define a connecting surface. The display panel couples with the connecting surface. An edge of the extending portion substantially aligns with or exceeds relative to the wall an edge of the display panel.

Abstract: An integrated circuit comprises a signal transmitter and a sampling circuit coupled to the signal transmitter, wherein the sampling circuit is to sample output voltage levels of an output of the signal transmitter at different respective times. The integrated circuit further comprises a measurement circuit coupled to the sampling circuit, wherein the measurement circuit is to compare the output voltage levels of the output of the signal transmitter to corresponding reference voltages to identify a first time when a first output voltage level equals a first reference voltage and a second time when a second output voltage level equals a second reference voltage. A time difference between the first time and the second time is used to configure a slew rate adjustment control of the signal transmitter.

Abstract: A semiconductor substrate includes a plurality of transistors. A first structure is disposed over a first side of the semiconductor substrate. The first structure contains a plurality of first metallization components. A carrier substrate is disposed over the first structure. The first structure is located between the carrier substrate and the semiconductor substrate. One or more openings extend through the carrier substrate and expose one or more regions of the first structure to the first side. A second structure is disposed over a second side of the semiconductor substrate opposite the first side. The second structure contains a plurality of second metallization components.

Abstract: A three-dimensional (3D) sound localization method, comprising: evaluating distances between a target object and multiple microphones; distinguishing a quadrant in which the target object is located; evaluating multiple elevation angles and azimuth angles of the target object according to spatial coordinates of each of the microphones; setting searching intervals of distance variables between the target object and each of the microphones; generating multiple test points according to the elevation angles, the azimuth angles and the searching intervals of the distance variables; calculating fitness of each of the test points; obtaining fitness values of each of the test points and comparing the fitness values between each of the test points; and, when a convergence condition is reached according to the fitness values, generating a positioning result of the target object.

Abstract: The application discloses a method applied in a system. The method includes the following operations: determining a first statistics of a first signal and a second statistics of a second signal according to a power split ratio and a noise level of a relay node; relaying, by the relay node, the first signal according to the power split ratio, the first statistics and the second statistics to generate the second signal; and receiving, by a destination node, the second signal.

Abstract: An apparatus including; a substrate; an isolator that is formed over the substrate, the isolator including a silicon shield layer that is formed between a first buried oxide (BOX) layer and a second BOX layer; a silicon layer having an oxide trench structure formed therein, the oxide trench structure being arranged to define a first silicon island and a second silicon island; a first electronic circuit that is formed over the first silicon island; and a second electronic circuit that is formed over the second silicon island, the first electronic circuit being electrically coupled to the first electronic circuit.

Abstract: An apparatus, comprising: a substrate; a coupling capacitor that is formed over the substrate; and an isolator that is formed between the substrate and the coupling capacitor, the isolator including: (a) an MP-well layer, (b) a first well layer, (c) an epi tub layer that is nested in the MP-well layer and the first well layer, and (d) a second well layer that is nested in the epi tub layer.

Abstract: A memory structure and its manufacturing method are provided. The memory structure includes a substrate, a tunnel dielectric layer on the substrate and a floating gate on the tunnel dielectric layer. The substrate has a source region and a drain region, and the source region and the drain region are formed on two opposite sides of the floating gate. The memory structure also includes an inter-gate dielectric layer on the floating gate and a control gate on the inter-gate dielectric layer. The memory structure further includes a doping region buried in the floating gate, wherein a sidewall of the doping region is exposed at a sidewall of the floating gate. Also, the doping region and the inter-gate dielectric layer are separated from each other.

Abstract: A three-dimensional (3D) sound localization method, comprising: evaluating distances between a target object and multiple microphones; distinguishing a quadrant in which the target object is located; evaluating multiple elevation angles and azimuth angles of the target object according to spatial coordinates of each of the microphones; setting searching intervals of distance variables between the target object and each of the microphones; generating multiple test points according to the elevation angles, the azimuth angles and the searching intervals of the distance variables; calculating fitness of each of the test points; obtaining fitness values of each of the test points and comparing the fitness values between each of the test points; and, when a convergence condition is reached according to the fitness values, generating a positioning result of the target object.

Abstract: An integrated circuit comprises a signal transmitter and a sampling circuit coupled to the signal transmitter, wherein the sampling circuit is to sample output voltage levels of an output of the signal transmitter at different respective times. The integrated circuit further comprises a measurement circuit coupled to the sampling circuit, wherein the measurement circuit is to compare the output voltage levels of the output of the signal transmitter to corresponding reference voltages to identify a first time when a first output voltage level equals a first reference voltage and a second time when a second output voltage level equals a second reference voltage. A time difference between the first time and the second time is used to configure a slew rate adjustment control of the signal transmitter.

Abstract: An apparatus, comprising: a substrate; a coupling capacitor that is formed over the substrate; and an isolator that is formed between the substrate and the coupling capacitor, the isolator including: (a) an MP-well layer, (b) a first well layer, (c) an epi tub layer that is nested in the MP-well layer and the first well layer, and (d) a second well layer that is nested in the epi tub layer.

Abstract: A horizontal pyrolysis furnace has a kiln and two barrels. The two barrels are respectively a processing barrel rotatably disposed in the kiln and a takeover barrel detachably connected with the processing barrel. Each one of the two barrels has a gate assembly and at least one spiral guiding plate. The gate assembly of the processing barrel is mounted on an end of the processing barrel, and extends out from the kiln. The two gate assemblies of the two barrels are detachably connected such that the two barrels are able to rotate synchronously. The at least one spiral guiding plate is fixed on an inner surface of one of the two barrels, and the spiral guiding plates of both barrels have an identical helical direction.

Abstract: A memory structure and its manufacturing method are provided. The memory structure includes a substrate, a tunnel dielectric layer on the substrate and a floating gate on the tunnel dielectric layer. The substrate has a source region and a drain region, and the source region and the drain region are formed on two opposite sides of the floating gate. The memory structure also includes an inter-gate dielectric layer on the floating gate and a control gate on the inter-gate dielectric layer. The memory structure further includes a doping region buried in the floating gate, wherein a sidewall of the doping region is exposed at a sidewall of the floating gate. Also, the doping region and the inter-gate dielectric layer are separated from each other.

Abstract: A horizontal pyrolysis furnace has a kiln and two barrels. The two barrels are respectively a processing barrel rotatably disposed in the kiln and a takeover barrel detachably connected with the processing barrel. Each one of the two barrels has a gate assembly and at least one spiral guiding plate. The gate assembly of the processing barrel is mounted on an end of the processing barrel, and extends out from the kiln. The two gate assemblies of the two barrels are detachably connected such that the two barrels are able to rotate synchronously. The at least one spiral guiding plate is fixed on an inner surface of one of the two barrels, and the spiral guiding plates of both barrels have an identical helical direction.

Abstract: The application discloses a method applied in a system. The method includes the following operations: determining a first statistics of a first signal and a second statistics of a second signal according to a power split ratio and a noise level of a relay node; relaying, by the relay node, the first signal according to the power split ratio, the first statistics and the second statistics to generate the second signal; and receiving, by a destination node, the second signal.

Abstract: An electronic waste processing apparatus has a power supply device, a vacuum cracking device, a filter device, and a separation device. The vacuum device is electrically connected to the power supply device, and has a vacuum pump, a vacuum chamber, and a high-frequency furnace body. The vacuum chamber is connected to and communicates with the vacuum pump. The high-frequency furnace body is disposed in the vacuum chamber. The filter device is electrically connected to the power supply device, and is connected to and communicates with the high-frequency furnace body of the vacuum cracking device. The separation device is electrically connected to the power supply device, is connected to and communicates with the vacuum pump and the filter device, and has a condensation cylinder, a cooling cylinder, and an oil storage tank.

Abstract: A slim linear LED lighting device is provided, including: a printed circuit board on which a connecting circuit is provided, at least one power input component, and a plurality of LED Bars. The LED Bar is formed by a plurality of the same kind of LED chips, and has a slim strip-shaped condensing lens structure integrally formed in the LED Bar packaging process by molding process to control the beam angle of the LED Bar and therefore the light distribution of the slim linear LED lighting device. The LED Bar's condensing lens has a small cross-sectional dimension; therefore the effective utilization factor of the light is improved as the slim linear LED lighting device is applied to a linear automotive lamp designed with a thin light blade structure.

Abstract: The present disclosure provides a resource allocation method. The resource allocation method includes the following steps: selecting multiple first selected virtual nodes according to multiple virtual pheromonal trails on multiple virtual edges, in which the first selected virtual nodes forms at least one virtual tour, and the virtual tour includes multiple first virtual edges; updating the virtual pheromonal trails on the virtual edges according to virtual distances corresponding to the first virtual edges of the virtual tour; selecting multiple second selected virtual nodes according to the updated virtual pheromonal trails on the virtual edges, in which the second selected virtual nodes form at least one resulting virtual tour; allocating the resource blocks to selected user pairs according to the resulting virtual tour.