Abstract: A Unified Protocol (UniPro) device with self functional test includes a physical layer circuit and a UniPro interface. The physical layer circuit has a transmit (TX) port and a receive (RX) port, wherein the TX port and the RX port are connected to each other via a loopback link under a self-test mode. The UniPro interface generates an outgoing test pattern to the TX port, and checks an incoming test pattern received from the RX port under the self-test mode.

Abstract: A Unified Protocol (UniPro) device with self functional test includes a physical layer circuit and a UniPro interface. The physical layer circuit has a transmit (TX) port and a receive (RX) port, wherein the TX port and the RX port are connected to each other via a loopback link under a self-test mode. The UniPro interface generates an outgoing test pattern to the TX port, and checks an incoming test pattern received from the RX port under the self-test mode.

Abstract: A data transceiving system, comprising: a data receiving apparatus, comprising a data receiving side command pin and at least one data receiving side data pin; a data transmitting apparatus, comprising a data transmitting side command pin and at least one data transmitting side data pin. The data receiving apparatus transmits a first command signal from the data receiving side command pin to the data transmitting side command pin, and the data transmitting apparatus transmits a first response signal from the data transmitting side command pin to the data receiving side command pin. The data transmitting apparatus transmits data from the data transmitting side data pin to the data receiving side data pin. The data transmitting apparatus transmits a first data sampling clock signal from the data transmitting side command pin to the data receiving side command pin, to sample the data.

Abstract: A data transceiving system, comprising: a data receiving apparatus, comprising a data receiving side command pin and at least one data receiving side data pin; a data transmitting apparatus, comprising a data transmitting side command pin and at least one data transmitting side data pin. The data receiving apparatus transmits a first command signal from the data receiving side command pin to the data transmitting side command pin, and the data transmitting apparatus transmits a first response signal from the data transmitting side command pin to the data receiving side command pin. The data transmitting apparatus transmits data from the data transmitting side data pin to the data receiving side data pin. The data transmitting apparatus transmits a first data sampling clock signal from the data transmitting side command pin to the data receiving side command pin, to sample the data.

Abstract: A method for Built-In Speed Grading (BISG) comprises a Circuit Under Test (CUT) with Built-In Self-Test (BIST) circuitry, an All-Digital Phase-Locked Loop (ADPLL), and a BISG, to automatically decide the maximum operating frequency of the CUT. The search process for this maximum operating frequency is conducted by a binary search in which the next frequency to test CUT is determined automatically by the BISG controller based on whether the CUT passes or fails the BIST session at current frequency. The maximum operating frequency the CUT can operate is narrowed down to a fine-tuning range out of a number of clock frequencies that the ADPLL can offer. The frequencies an ADPLL can offer is divided into a plurality of coarse ranges, with each of them further having a plurality of fine-tuning frequencies.